公开(公告)号：US20120293699A1

公开(公告)日：2012-11-22

申请号：US13109231

申请日：2011-05-17

Applicant: Laurent Blanquart ,  John Wallner ,  Manjunath Bhat

Inventor： Laurent Blanquart ,  John Wallner ,  Manjunath Bhat

IPC: H04N5/335

CPC classification number: H04N5/3535 ,  H04N5/374

Abstract: Providing for pausing data readout from an optical sensor array is described herein. By way of example, an interruption period can be introduced into a readout cycle of the optical sensor array to suspend readout of data. During the interruption period, other operations related to the optical sensor array can be performed, including operations that are typically detrimental to image quality. Moreover, these operations can be performed while mitigating or avoiding negative impact on the image quality. Thus, greater flexibility is provided for global shutter operations, for instance, potentially improving frame rates and fine control of image exposure, while preserving image quality.

Abstract translation: 这里描述了从光学传感器阵列暂停数据读出。 作为示例，可以将中断周期引入光学传感器阵列的读出周期以暂停数据的读出。 在中断期间，可以执行与光学传感器阵列相关的其它操作，包括通常对图像质量有害的操作。 此外，可以在减轻或避免图像质量的负面影响的同时执行这些操作。 因此，为全局快门操作提供更大的灵活性，例如，可以在保持图像质量的同时潜在地提高帧速率和图像曝光的精细控制。

公开(公告)号：US08823846B2

公开(公告)日：2014-09-02

申请号：US13109231

申请日：2011-05-17

Applicant: Laurent Blanquart ,  John Wallner ,  Manjunath Bhat

Inventor： Laurent Blanquart ,  John Wallner ,  Manjunath Bhat

IPC: H04N3/14 ,  H04N5/335

CPC classification number: H04N5/3535 ,  H04N5/374

Abstract: Providing for pausing data readout from an optical sensor array is described herein. By way of example, an interruption period can be introduced into a readout cycle of the optical sensor array to suspend readout of data. During the interruption period, other operations related to the optical sensor array can be performed, including operations that are typically detrimental to image quality. Moreover, these operations can be performed while mitigating or avoiding negative impact on the image quality. Thus, greater flexibility is provided for global shutter operations, for instance, potentially improving frame rates and fine control of image exposure, while preserving image quality.

Abstract translation: 这里描述了从光学传感器阵列暂停数据读出。 作为示例，可以将中断周期引入光学传感器阵列的读出周期以暂停数据的读出。 在中断期间，可以执行与光学传感器阵列相关的其它操作，包括通常对图像质量有害的操作。 此外，可以在减轻或避免图像质量的负面影响的同时执行这些操作。 因此，为全局快门操作提供更大的灵活性，例如，可以在保持图像质量的同时潜在地提高帧速率和图像曝光的精细控制。

公开(公告)号：US07227384B2

公开(公告)日：2007-06-05

申请号：US11201559

申请日：2005-08-11

Applicant: Mondira Pant ,  Paul Gronowski ,  Randy Allmon ,  Manjunath Bhat ,  David Lin

Inventor： Mondira Pant ,  Paul Gronowski ,  Randy Allmon ,  Manjunath Bhat ,  David Lin

IPC: H03K19/20

CPC classification number: H03K19/0963 ,  G01R31/318572

Abstract: A circuit for converting received domino logic signals to a static output signal includes a pair of logic gates having inputs and outputs that are cross-coupled and responsive to a domino logic input signal and a clock signal to latch the input signal during an evaluation phase defined by the clock signal. A static output is based on the latched value. One of the logic gates is tri-stateable to establish a value at the static output during a scan mode. A circuit for converting received static logic signals into domino logic signals includes a latch responsive to a clock signal to latch the value of a data signal at a predefined clock transition. A conversion circuit produces a domino logic output signal in response to the clock signal and the latched value of the data signal. A latch component is tri-stateable to establish a value at the output.

Abstract translation: 用于将接收的多米诺骨牌逻辑信号转换成静态输出信号的电路包括一对逻辑门，其具有交叉耦合的输入和输出，并且响应于多米诺逻辑输入信号和时钟信号，以在定义的评估阶段期间锁存输入信号 通过时钟信号。 静态输出基于锁存值。 逻辑门之一是在扫描模式期间在静态输出处建立一个值的三态。 用于将接收到的静态逻辑信号转换为多米诺逻辑信号的电路包括响应于时钟信号的锁存器，以在预定义的时钟转换时锁存数据信号的值。 转换电路响应于时钟信号和数据信号的锁存值产生多米诺逻辑输出信号。 锁存器组件是三态的以在输出端建立一个值。

公开(公告)号：US20070035331A1

公开(公告)日：2007-02-15

申请号：US11201559

申请日：2005-08-11

Applicant: Mondira Pant ,  Paul Gronowski ,  Randy Allmon ,  Manjunath Bhat ,  David Lin

Inventor： Mondira Pant ,  Paul Gronowski ,  Randy Allmon ,  Manjunath Bhat ,  David Lin

IPC: H03K19/096

CPC classification number: H03K19/0963 ,  G01R31/318572

Abstract: A circuit for converting received domino logic signals to a static output signal includes a pair of logic gates having inputs and outputs that are cross-coupled and responsive to a domino logic input signal and a clock signal to latch the input signal during an evaluation phase defined by the clock signal. A static output is based on the latched value. One of the logic gates is tri-stateable to establish a value at the static output during a scan mode. A circuit for converting received static logic signals into domino logic signals includes a latch responsive to a clock signal to latch the value of a data signal at a predefined clock transition. A conversion circuit produces a domino logic output signal in response to the clock signal and the latched value of the data signal. A latch component is tri-stateable to establish a value at the output.