公开(公告)号：US07227384B2

公开(公告)日：2007-06-05

申请号：US11201559

申请日：2005-08-11

申请人： Mondira Pant ,  Paul Gronowski ,  Randy Allmon ,  Manjunath Bhat ,  David Lin

发明人： Mondira Pant ,  Paul Gronowski ,  Randy Allmon ,  Manjunath Bhat ,  David Lin

IPC分类号： H03K19/20

CPC分类号： H03K19/0963 ,  G01R31/318572

摘要： A circuit for converting received domino logic signals to a static output signal includes a pair of logic gates having inputs and outputs that are cross-coupled and responsive to a domino logic input signal and a clock signal to latch the input signal during an evaluation phase defined by the clock signal. A static output is based on the latched value. One of the logic gates is tri-stateable to establish a value at the static output during a scan mode. A circuit for converting received static logic signals into domino logic signals includes a latch responsive to a clock signal to latch the value of a data signal at a predefined clock transition. A conversion circuit produces a domino logic output signal in response to the clock signal and the latched value of the data signal. A latch component is tri-stateable to establish a value at the output.

摘要翻译： 用于将接收的多米诺骨牌逻辑信号转换成静态输出信号的电路包括一对逻辑门，其具有交叉耦合的输入和输出，并且响应于多米诺逻辑输入信号和时钟信号，以在定义的评估阶段期间锁存输入信号 通过时钟信号。 静态输出基于锁存值。 逻辑门之一是在扫描模式期间在静态输出处建立一个值的三态。 用于将接收到的静态逻辑信号转换为多米诺逻辑信号的电路包括响应于时钟信号的锁存器，以在预定义的时钟转换时锁存数据信号的值。 转换电路响应于时钟信号和数据信号的锁存值产生多米诺逻辑输出信号。 锁存器组件是三态的以在输出端建立一个值。

公开(公告)号：US20070035331A1

公开(公告)日：2007-02-15

申请号：US11201559

申请日：2005-08-11

申请人： Mondira Pant ,  Paul Gronowski ,  Randy Allmon ,  Manjunath Bhat ,  David Lin

发明人： Mondira Pant ,  Paul Gronowski ,  Randy Allmon ,  Manjunath Bhat ,  David Lin

IPC分类号： H03K19/096

CPC分类号： H03K19/0963 ,  G01R31/318572

摘要： A circuit for converting received domino logic signals to a static output signal includes a pair of logic gates having inputs and outputs that are cross-coupled and responsive to a domino logic input signal and a clock signal to latch the input signal during an evaluation phase defined by the clock signal. A static output is based on the latched value. One of the logic gates is tri-stateable to establish a value at the static output during a scan mode. A circuit for converting received static logic signals into domino logic signals includes a latch responsive to a clock signal to latch the value of a data signal at a predefined clock transition. A conversion circuit produces a domino logic output signal in response to the clock signal and the latched value of the data signal. A latch component is tri-stateable to establish a value at the output.