发明申请
US20070043991A1 Deserializer circuitry for high-speed serial data receivers on programmable logic device integrated circuits
有权
用于可编程逻辑器件集成电路上的高速串行数据接收器的解串器电路
- 专利标题： Deserializer circuitry for high-speed serial data receivers on programmable logic device integrated circuits
- 专利标题（中）： 用于可编程逻辑器件集成电路上的高速串行数据接收器的解串器电路
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申请号： US11359273申请日： 2006-02-21
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公开(公告)号： US20070043991A1公开(公告)日： 2007-02-22
- 发明人: Toan Nguyen , Thungoc Tran , Sergey Shumarayev , Arch Zaliznyak , Tim Hoang , Ramanand Venkata , Chong Lee
- 申请人： Toan Nguyen , Thungoc Tran , Sergey Shumarayev , Arch Zaliznyak , Tim Hoang , Ramanand Venkata , Chong Lee
- 专利权人： Altera Corporation
- 当前专利权人： Altera Corporation
- 主分类号： G01R31/28
- IPC分类号： G01R31/28
摘要：
Deserializer circuitry for high-speed serial data receiver circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting serial data to parallel data having any of several data widths. The circuitry can also operate at any frequency in a wide range of frequencies. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).