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    Methods and apparatus to DC couple LVDS driver to CML levels
    1.
    发明申请
    Methods and apparatus to DC couple LVDS driver to CML levels 有权
    将LVDS驱动程序直接耦合到CML级别的方法和设备

    公开(公告)号：US20060220681A1

    公开(公告)日：2006-10-05

    申请号：US11098832

    申请日：2005-04-04

    申请人： Wilson Wong ,  Tim Hoang ,  Sergey Shumarayev ,  Rakesh Patel ,  Simardeep Maangat

    发明人： Wilson Wong ,  Tim Hoang ,  Sergey Shumarayev ,  Rakesh Patel ,  Simardeep Maangat

    IPC分类号： H03K19/094

    CPC分类号： H03K19/017545

    摘要： Circuitry and methods are provided for an LVDS-like transmitter that may be able to DC couple to a receiver having a CML termination scheme. Replacing the common mode voltage source of an LVDS transmitter with a resistive pulldown to ground may allow the transmitter to interface in a DC coupled fashion with a CML receiver. Further, the resistive pulldown may be programmable. This LVDS-like transmitter may be able to support a wider customer base by allowing it to DC couple to a wider range of termination voltage levels, such as CML termination voltage levels.

    摘要翻译： 为能够将DC耦合到具有CML终止方案的接收机的类似LVDS的发射机提供电路和方法。 将具有电阻下拉到地的LVDS发射机的共模电压源替换可允许发射机以直流耦合方式与CML接收器接口。 此外，电阻下拉可以是可编程的。 这种类似LVDS的发射机可能能够通过允许其将DC耦合到更广泛的终止电压电平范围（例如CML终止电压电平）来支持更广泛的客户群。

    Modular interconnect circuitry for multi-channel transceiver clock signals
    2.
    发明申请
    Modular interconnect circuitry for multi-channel transceiver clock signals 有权
    用于多通道收发器时钟信号的模块化互连电路

    公开(公告)号：US20070018863A1

    公开(公告)日：2007-01-25

    申请号：US11270718

    申请日：2005-11-08

    申请人： Tim Hoang ,  Sergey Shumarayev

    发明人： Tim Hoang ,  Sergey Shumarayev

    IPC分类号： H03M9/00

    CPC分类号： G06F1/10 ,  H03K19/177 ,  H03K19/17736

    摘要： Circuitry for distributing clock signals (e.g., reference clock signals) among a plurality of blocks of circuitry. Each block may include reference clock source circuitry and reference clock utilization circuitry. Each block also preferably includes an identical or substantially identical module of clock signal distribution circuitry that can (1) accept a signal from the source circuitry in that block, (2) apply any of several clock signals to the utilization circuitry in that block, and (3) connect to the similar module(s) of one or more adjacent blocks.

    摘要翻译： 用于在多个电路块之间分配时钟信号（例如，参考时钟信号）的电路。 每个块可以包括参考时钟源电路和参考时钟利用电路。 每个块还优选地包括相同或基本相同的时钟信号分配电路模块，其可以（1）接收来自该块中的源电路的信号，（2）将几个时钟信号中的任何一个应用于该块中的利用电路，以及 （3）连接到一个或多个相邻块的相似模块。

    ENHANCED PASSGATE STRUCTURES FOR REDUCING LEAKAGE CURRENT
    3.
    发明申请
    ENHANCED PASSGATE STRUCTURES FOR REDUCING LEAKAGE CURRENT 有权
    用于降低泄漏电流的增强通孔结构

    公开(公告)号：US20060028240A1

    公开(公告)日：2006-02-09

    申请号：US10910891

    申请日：2004-08-03

    申请人： Henry Lui ,  Malik Kabani ,  Rakesh Patel ,  Tim Hoang

    发明人： Henry Lui ,  Malik Kabani ,  Rakesh Patel ,  Tim Hoang

    IPC分类号： H03K19/173

    CPC分类号： H03K19/1778 ,  H03K19/17784 ,  H03K19/17792

    摘要： Enhanced passgate structures for use in low-voltage systems are presented in which the operational speed of the passgate structures is maximized, while minimizing leakage current when the structure is turned “OFF.” In one arrangement, the VT of the pass-gate structures is increased relative to the VT of other transistors fabricated according to a particular process dimension. In addition, a passgate activation voltage is applied to the passgate structures such that the passgate activation voltage is higher in voltage than a nominal voltage being supplied to circuitry other than the passgate structures.

    摘要翻译： 提出了在低压系统中使用的增强型门控结构，其中通道结构的操作速度最大化，同时使结构“OFF”时的漏电流最小化。 在一种布置中，栅极结构的栅极相对于根据特定工艺尺寸制造的其它晶体管的V IN T T T T增加。 此外，通道激活电压被施加到通道结构，使得通电门激活电压的电压高于提供给非门电路结构以外的电路的标称电压。

    Multi-channel communication circuitry for programmable logic device integrated circuits and the like
    4.
    发明申请
    Multi-channel communication circuitry for programmable logic device integrated circuits and the like 有权
    用于可编程逻辑器件集成电路等的多通道通信电路

    公开(公告)号：US20070058618A1

    公开(公告)日：2007-03-15

    申请号：US11288810

    申请日：2005-11-28

    申请人： Thungoc Tran ,  Sergey Shumarayev ,  Tim Hoang ,  Ning Xue ,  Chong Lee ,  Ramanand Venkata

    发明人： Thungoc Tran ,  Sergey Shumarayev ,  Tim Hoang ,  Ning Xue ,  Chong Lee ,  Ramanand Venkata

    IPC分类号： H04L12/50

    CPC分类号： H03K19/17736 ,  H03K19/17744

    摘要： An integrated circuit like a programmable logic device (“PLD”) includes multiple channels of data communication circuitry. Circuitry is provided for selectively sharing signals (e.g., control-type signals) among these channels in groupings of various size so that the device can better support communication protocols that require various numbers of channels (e.g., one channel operating relatively independently, four channels working together, eight channels working together, etc.). The signals shared may include a clock signal, a FIFO write enable signal, a FIFO read enable signal, or the like. The circuit arrangements are preferably modular (i.e., the same or substantially the same from one channel to the next and/or from one group of channels to the next) to facilitate such things as circuit design and verification.

    摘要翻译： 诸如可编程逻辑器件（“PLD”）的集成电路包括多个通道的数据通信电路。 提供电路用于在各种尺寸的分组中选择性地共享这些信道中的信号（例如，控制型信号），使得设备可以更好地支持需要各种信道数量的通信协议（例如，一个信道相对独立地操作，四个信道工作 一起，八个渠道在一起等）。 共享的信号可以包括时钟信号，FIFO写使能信号，FIFO读使能信号等。 电路布置优选地是模块化的（即，从一个通道到下一个通道和/或从一组通道到下一个通道相同或基本相同），以促进诸如电路设计和验证的事情。