公开(公告)号：US09515880B1

公开(公告)日：2016-12-06

申请号：US13338898

申请日：2011-12-28

Applicant: Ramanand Venkata ,  Henry Y. Lui ,  Victor Maruri ,  David W. Mendel ,  Andrew Bellis

Inventor： Ramanand Venkata ,  Henry Y. Lui ,  Victor Maruri ,  David W. Mendel ,  Andrew Bellis

IPC: G06F15/177 ,  G06F1/00 ,  G06F1/04 ,  G06F15/16 ,  H04L12/24 ,  G06F1/10 ,  G06F17/50 ,  G06F9/445

CPC classification number: H04L41/0816 ,  G06F1/04 ,  G06F1/10 ,  G06F9/44505 ,  G06F17/5054 ,  H04J3/0688 ,  H04J3/0691 ,  H04J3/0697 ,  H04L41/0813

Abstract: An integrated circuit device may include processing circuits that can be dynamically reconfigured to perform different tasks each of which utilizes different system clock resources. The device may include clock selection circuitry that can selectively route desired clock signals to corresponding processing circuits. The clock signal provided to each processing circuit may be selected based on a current configuration of that processing circuit. Client processing circuits in a network switch may be coupled to interchangeable client networks. The client processing circuits may be dynamically reconfigured based on characteristics of the client networks that are currently coupled to the network switch. By dynamically selecting which clock resources are provided to the processing circuits, clock resources such as global clock signals that are relatively scarce may be reserved for processing circuits that can only function with the relatively scarce clock resources. Arranged in this way, clock resource utilization may be continuously optimized.

Abstract translation: 集成电路设备可以包括可以动态地重新配置以执行不同的任务的处理电路，每个任务利用不同的系统时钟资源。 该装置可以包括时钟选择电路，其可以选择性地将期望的时钟信号路由到相应的处理电路。 可以基于该处理电路的当前配置来选择提供给每个处理电路的时钟信号。 网络交换机中的客户端处理电路可以耦合到可互换的客户端网络。 可以基于当前耦合到网络交换机的客户端网络的特性来动态地重新配置客户端处理电路。 通过动态地选择哪些时钟资源被提供给处理电路，诸如相对稀少的全局时钟信号的时钟资源可以被保留用于只能用相对稀少的时钟资源起作用的处理电路。 以这种方式安排，可以不断优化时钟资源利用。

公开(公告)号：US07659838B2

公开(公告)日：2010-02-09

申请号：US11359273

申请日：2006-02-21

Applicant: Toan Thanh Nguyen ,  Thungoc Tran ,  Sergey Yuryevich Shumarayev ,  Arch Zaliznyak ,  Tim Tri Hoang ,  Ramanand Venkata ,  Chong Lee

Inventor： Toan Thanh Nguyen ,  Thungoc Tran ,  Sergey Yuryevich Shumarayev ,  Arch Zaliznyak ,  Tim Tri Hoang ,  Ramanand Venkata ,  Chong Lee

IPC: H03M9/00

CPC classification number: H03M9/00

Abstract: Deserializer circuitry for high-speed serial data receiver circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting serial data to parallel data having any of several data widths. The circuitry can also operate at any frequency in a wide range of frequencies. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).

Abstract translation: 用于可编程逻辑器件（“PLD”）等上的高速串行数据接收器电路的解串器电路包括用于将串行数据转换成具有若干数据宽度的并行数据的电路。 电路也可以在宽频率范围内的任何频率下工作。 该电路在各个方面是可配置的/可重新配置的，其中至少一些配置/重新配置可被动态地控制（即在PLD的用户模式操作期间）。

公开(公告)号：US20070011370A1

公开(公告)日：2007-01-11

申请号：US11177007

申请日：2005-07-08

Applicant: Ramanand Venkata ,  Rakesh Patel ,  Chong Lee

Inventor： Ramanand Venkata ,  Rakesh Patel ,  Chong Lee

IPC: G06F13/38

CPC classification number: H03K19/17744

Abstract: A serial interface for a programmable logic device supports a wide range of data rates by providing a first number of channels supporting a first range of data rates and a second number of channels supporting a second range of data rates. The first range of data rates is preferably lower than the second range of data rates and preferably the first number of channels is higher than the second number of channels which preferably is 1. For backward compatibility with existing devices, the first number of channels in each interface preferably is four. Each channel preferably includes a physical medium attachment module and a physical coding sublayer module. Each of the higher-speed channels in the second number of channels preferably also includes a clock management unit, while the lower-speed channels in the first number of channels preferably share one or more clock management units.

Abstract translation: 用于可编程逻辑器件的串行接口通过提供支持第一范围的数据速率的第一数量的通道和支持第二数据速率范围的第二数量的通道来支持宽范围的数据速率。 数据速率的第一范围优选地低于数据速率的第二范围，并且优选地，第一数量的信道高于优选为1的信道的第二数量。为了与现有设备的向后兼容，每个信道中的第一数量的信道 界面最好是四。 每个通道优选地包括物理介质连接模块和物理编码子层模块。 第二数量的频道中的每一个较高频道优选地还包括时钟管理单元，而第一数量的频道中的较低速频道优选地共享一个或多个时钟管理单元。

公开(公告)号：US07039787B1

公开(公告)日：2006-05-02

申请号：US10984684

申请日：2004-11-09

Applicant: Ramanand Venkata ,  Chong H. Lee

Inventor： Ramanand Venkata ,  Chong H. Lee

IPC: G06F12/00

CPC classification number: G06F13/4018 ,  H04J3/0608

Abstract: Circuitry for locating the boundaries between bytes in a data stream is only selectively enabled to find a possible new byte alignment by a control signal. After the byte alignment circuitry has found a byte alignment, it outputs byte-aligned data and a first status signal indicating the presence of such data. If the byte alignment circuitry subsequently detects information that suggests a possible need for a new or changed byte alignment, it outputs a second status signal to that effect. However, the byte alignment circuitry does not actually attempt to change its byte alignment until enabled to do so by the control signal. Programmable logic circuitry or other utilization circuitry is typically provided to receive the outputs of the byte alignment circuitry and to selectively provide the control signal.

Abstract translation: 用于定位数据流中的字节之间的边界的电路仅被选择性地用于通过控制信号找到可能的新字节对齐。 在字节对齐电路找到一个字节对齐之后，它输出字节对齐的数据和指示这种数据的存在的第一状态信号。 如果字节对齐电路随后检测到提示可能需要新的或改变的字节对齐的信息，则输出第二状态信号。 然而，字节对齐电路实际上并不会尝试改变其字节对齐，直到通过控制信号使其能够这样做。 通常提供可编程逻辑电路或其他利用电路以接收字节对准电路的输出并选择性地提供控制信号。

公开(公告)号：US20060012394A1

公开(公告)日：2006-01-19

申请号：US11189209

申请日：2005-07-26

Applicant: Ramanand Venkata ,  Chong Lee ,  Rakesh Patel

Inventor： Ramanand Venkata ,  Chong Lee ,  Rakesh Patel

IPC: H03K19/177

CPC classification number: H03K19/17744 ,  H03K19/17732 ,  H04J3/1617 ,  H04J2203/0082 ,  H04J2203/0094

Abstract: A programmable logic device (“PLD”) includes communication interface circuitry that can support any of a wide range of communication protocols, including Packet Over Sonet (“POS-5”) and 8-bit/10-bit (“8B10B”) protocols. The interface circuitry includes various functional blocks that are at least partly hard-wired to perform particular types of functions, but that in at least many cases are also partly programmable to allow the basic functions to be adapted for various protocols. Routing of signals to, from, between, and/or around the various functional blocks is also preferably at least partly programmable to facilitate combining the functional blocks in various ways to support various protocols.

公开(公告)号：US06867616B1

公开(公告)日：2005-03-15

申请号：US10455773

申请日：2003-06-04

Applicant: Ramanand Venkata ,  Chong H. Lee ,  Rakesh Patel

Inventor： Ramanand Venkata ,  Chong H. Lee ,  Rakesh Patel

IPC: H03K19/177 ,  H03K19/173 ,  H03D3/24

CPC classification number: H03K19/17736 ,  H03K19/1774 ,  H03K19/17744

Abstract: In a programmable logic device (“PLD”), a serial interface incorporating phase-locked loops (“PLLs”) is provided with connections that allow one or more of the PLLs to be used as general purpose PLLs in the PLD. The connections include conductors to allow reference clock signals from the PLD logic core, or from outside the PLL, to be used by the PLLS, as well as conductors that allow the PLD core to control the phases of the PLLs. For some of the PLLs, conductors to allow the PLL output clock to be used by the PLD are also provided, where such output conductors do not normally exist in such a serial interface.

Abstract translation: 在可编程逻辑器件（“PLD”）中，集成了锁相环（“PLL”）的串行接口具有允许一个或多个PLL用作PLD中的通用PLL的连接。 这些连接包括允许来自PLD逻辑核心或PLL外部的参考时钟信号由PLLS使用的导体以及允许PLD内核控制PLL相位的导体。 对于一些PLL，还提供允许PLD使用PLL输出时钟的导体，其中这种输出导体通常不存在于这种串行接口中。

公开(公告)号：US08994425B2

公开(公告)日：2015-03-31

申请号：US13566882

申请日：2012-08-03

Applicant: Ramanand Venkata ,  Henry Lui ,  Arch Zaliznyak

Inventor： Ramanand Venkata ,  Henry Lui ,  Arch Zaliznyak

IPC: H03L7/00 ,  H03K5/1534

CPC classification number: H03K5/1534

Abstract: A circuit includes first and second aligner circuits and a deskew circuit. The first aligner circuit is operable to align a first input serial data signal with a control signal to generate a first aligned serial data signal. The second aligner circuit is operable to align a second input serial data signal with the control signal to generate a second aligned serial data signal. The deskew circuit is operable to reduce skew between the first and the second aligned serial data signals to generate first and second output serial data signals.

Abstract translation: 一个电路包括第一和第二对准器电路和一个去歪斜电路。 第一对准器电路可操作以将第一输入串行数据信号与控制信号对准以产生第一对准的串行数据信号。 第二对准器电路可操作以将第二输入串行数据信号与控制信号对准以产生第二对准的串行数据信号。 去偏置电路可操作以减少第一和第二对准的串行数据信号之间的偏差，以产生第一和第二输出串行数据信号。

公开(公告)号：US08812893B1

公开(公告)日：2014-08-19

申请号：US13486482

申请日：2012-06-01

Applicant: Ramanand Venkata ,  Henry Y. Lui

Inventor： Ramanand Venkata ,  Henry Y. Lui

IPC: G06F1/04 ,  H03K21/00

CPC classification number: H03K21/38 ,  G06F1/10 ,  G06F1/24

Abstract: One embodiment relates an apparatus which includes a plurality of local synchronous divider circuits, each local synchronous divider circuit being configured to receive a serial clock signal and a reset signal and generate a local clock signal. The apparatus further includes a clock distribution network configured to distribute the serial clock signal to the plurality of local synchronous divider circuits and a signal distribution network configured to distribute the reset signal to the plurality of local synchronous divider circuits. Another embodiment relates to a method of distributing a serial clock signal and a reset signal to a plurality of local synchronous divider circuits and generating a local clock signal at each of the plurality of local synchronous divider circuits. Other embodiments, aspects, and features are also disclosed.

Abstract translation: 一个实施例涉及一种包括多个本地同步分配器电路的设备，每个本地同步分配器电路被配置为接收串行时钟信号和复位信号并产生本地时钟信号。 该装置还包括时钟分配网络，其被配置为将串行时钟信号分配给多个本地同步分频器电路，以及信号分配网络，配置为将复位信号分配给多个本地同步分频器电路。 另一实施例涉及一种将串行时钟信号和复位信号分配给多个本地同步分频器电路并在多个本地同步分配器电路中的每一个产生本地时钟信号的方法。 还公开了其它实施例，方面和特征。

公开(公告)号：US08570197B2

公开(公告)日：2013-10-29

申请号：US12953766

申请日：2010-11-24

Applicant: Toan Thanh Nguyen ,  Thungoc Tran ,  Sergey Yuryevich Shumarayev ,  Arch Zaliznyak ,  Shoujun Wang ,  Ramanand Venkata ,  Chong Lee

Inventor： Toan Thanh Nguyen ,  Thungoc Tran ,  Sergey Yuryevich Shumarayev ,  Arch Zaliznyak ,  Shoujun Wang ,  Ramanand Venkata ,  Chong Lee

IPC: H03M9/00

CPC classification number: H03K19/00 ,  H03K19/17744 ,  H03M9/00 ,  H04L1/243 ,  H04L7/0008 ,  H04L7/033 ,  H04L25/0266

Abstract: Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).

Abstract translation: 用于可编程逻辑器件（“PLD”）等上的高速串行数据发射器电路的串行器电路包括用于将具有若干数据宽度中的任一个的并行数据转换为串行数据的电路。 电路还可以在宽频率范围内的任何频率下操作，并且可以利用具有与并行数据速率和/或串行数据速率的几个关系中的任何一个的参考时钟信号。 该电路在各个方面是可配置的/可重新配置的，其中至少一些配置/重新配置可被动态地控制（即在PLD的用户模式操作期间）。

公开(公告)号：US07656187B2

公开(公告)日：2010-02-02

申请号：US11288810

申请日：2005-11-28

Applicant: Thungoc Tran ,  Sergey Yuryevich Shumarayev ,  Tim Tri Hoang ,  Ning Xue ,  Chong Lee ,  Ramanand Venkata

Inventor： Thungoc Tran ,  Sergey Yuryevich Shumarayev ,  Tim Tri Hoang ,  Ning Xue ,  Chong Lee ,  Ramanand Venkata

IPC: H03K19/173

CPC classification number: H03K19/17736 ,  H03K19/17744

Abstract: An integrated circuit like a programmable logic device (“PLD”) includes multiple channels of data communication circuitry. Circuitry is provided for selectively sharing signals (e.g., control-type signals) among these channels in groupings of various size so that the device can better support communication protocols that require various numbers of channels (e.g., one channel operating relatively independently, four channels working together, eight channels working together, etc.). The signals shared may include a clock signal, a FIFO write enable signal, a FIFO read enable signal, or the like. The circuit arrangements are preferably modular (i.e., the same or substantially the same from one channel to the next and/or from one group of channels to the next) to facilitate such things as circuit design and verification.

Abstract translation: 诸如可编程逻辑器件（“PLD”）的集成电路包括多个通道的数据通信电路。 提供电路用于在各种尺寸的分组中选择性地共享这些信道中的信号（例如，控制型信号），使得设备可以更好地支持需要各种信道数量的通信协议（例如，一个信道相对独立地操作，四个信道工作 一起，八个渠道在一起等）。 共享的信号可以包括时钟信号，FIFO写使能信号，FIFO读使能信号等。 电路布置优选地是模块化的（即，从一个通道到下一个通道和/或从一组通道到下一个通道相同或基本相同），以便于诸如电路设计和验证之类的事情。