- 专利标题: Flash memory array system including a top gate memory cell
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申请号: US11235901申请日: 2005-09-26
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公开(公告)号: US20070070703A1公开(公告)日: 2007-03-29
- 发明人: Hieu Tran , Hung Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Nguyen , Loc Hoang , Steve Choi , Thuan Vu
- 申请人: Hieu Tran , Hung Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Nguyen , Loc Hoang , Steve Choi , Thuan Vu
- 主分类号: G11C11/34
- IPC分类号: G11C11/34
摘要:
A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.