发明申请
- 专利标题: LOW-COST FEOL FOR ULTRA-LOW POWER, NEAR SUB-VTH DEVICE STRUCTURES
- 专利标题(中): 低功耗超低功耗,小型设备结构
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申请号: US11164651申请日: 2005-11-30
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公开(公告)号: US20070122957A1公开(公告)日: 2007-05-31
- 发明人: Brent Anderson , Andres Bryant , William Clark , Jeffrey Gambino , Shih-Fen Huang , Edward Nowak , Anthony Stamper
- 申请人: Brent Anderson , Andres Bryant , William Clark , Jeffrey Gambino , Shih-Fen Huang , Edward Nowak , Anthony Stamper
- 申请人地址: US NY Armonk
- 专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人地址: US NY Armonk
- 主分类号: H01L21/8234
- IPC分类号: H01L21/8234 ; H01L29/76 ; H01L21/336
摘要:
In order to reduce power dissipation requirements, obtain full potential transistor performance and avoid power dissipation limitations on transistor performance in high density integrated circuits, transistors are operated in a sub-threshold (sub-Vth) or a near sub-Vth voltage regime (generally about 0.2 volts rather than a super-Vth regime of about 1.2 volts or higher) and optimized for such operation, particularly through simplification of the transistor structure, since intrinsic channel resistance is dominant in sub-Vth operating voltage regimes. Such simplifications include an underlap or recess of the source and drain regions from the gate which avoids overlap capacitance to partially recover loss of switching speed otherwise caused by low voltage operation, an ultra-thin gate structure having a thickness of 500 Å or less which also simplifies forming connections to the transistor and an avoidance of silicidation or alloy formation in the source, drain and/or gate of transistors.