公开(公告)号：US20070122957A1

公开(公告)日：2007-05-31

申请号：US11164651

申请日：2005-11-30

申请人： Brent Anderson ,  Andres Bryant ,  William Clark ,  Jeffrey Gambino ,  Shih-Fen Huang ,  Edward Nowak ,  Anthony Stamper

发明人： Brent Anderson ,  Andres Bryant ,  William Clark ,  Jeffrey Gambino ,  Shih-Fen Huang ,  Edward Nowak ,  Anthony Stamper

IPC分类号： H01L21/8234 ,  H01L29/76 ,  H01L21/336

CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78

摘要： In order to reduce power dissipation requirements, obtain full potential transistor performance and avoid power dissipation limitations on transistor performance in high density integrated circuits, transistors are operated in a sub-threshold (sub-Vth) or a near sub-Vth voltage regime (generally about 0.2 volts rather than a super-Vth regime of about 1.2 volts or higher) and optimized for such operation, particularly through simplification of the transistor structure, since intrinsic channel resistance is dominant in sub-Vth operating voltage regimes. Such simplifications include an underlap or recess of the source and drain regions from the gate which avoids overlap capacitance to partially recover loss of switching speed otherwise caused by low voltage operation, an ultra-thin gate structure having a thickness of 500 Å or less which also simplifies forming connections to the transistor and an avoidance of silicidation or alloy formation in the source, drain and/or gate of transistors.

摘要翻译： 为了降低功耗要求，获得全电位晶体管性能并避免在高密度集成电路中对晶体管性能的功率限制，晶体管以子阈值（sub-V thth th）或 接近次级V th电压方式（通常约为0.2伏，而不是大于1.2伏特或更高的超V 2），并且针对这种操作进行了优化，特别是通过简化 的晶体管结构，因为固有沟道电阻在次级V 3工作电压方面是主要的。 这种简化包括来自栅极的源极和漏极区域的欠叠或凹陷，其避免重叠电容以部分恢复由低电压操作引起的切换速度的损失，厚度为或等于或小于500埃的超薄栅极结构 简化了与晶体管的形成连接，避免了晶体管的源极，漏极和/或栅极中的硅化或合金形成。

公开(公告)号：US07816738B2

公开(公告)日：2010-10-19

申请号：US11164651

申请日：2005-11-30

申请人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, Jr. ,  Jeffrey P. Gambino ,  Shih-Fen Huang ,  Edward J. Nowak ,  Anthony K. Stamper

发明人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, Jr. ,  Jeffrey P. Gambino ,  Shih-Fen Huang ,  Edward J. Nowak ,  Anthony K. Stamper

IPC分类号： H01L27/088

CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78

摘要： In order to reduce power dissipation requirements, obtain full potential transistor performance and avoid power dissipation limitations on transistor performance in high density integrated circuits, transistors are operated in a sub-threshold (sub-Vth) or a near sub-Vth voltage regime (generally about 0.2 volts rather than a super-Vth regime of about 1.2 volts or higher) and optimized for such operation, particularly through simplification of the transistor structure, since intrinsic channel resistance is dominant in sub-Vth operating voltage regimes. Such simplifications include an underlap or recess of the source and drain regions from the gate which avoids overlap capacitance to partially recover loss of switching speed otherwise caused by low voltage operation, an ultra-thin gate structure having a thickness of 500 Å or less which also simplifies forming connections to the transistor and an avoidance of silicidation or alloy formation in the source, drain and/or gate of transistors.

摘要翻译： 为了降低功耗要求，获得全电位晶体管性能，并避免在高密度集成电路中对晶体管性能的功耗限制，晶体管工作在亚阈值（sub-Vth）或接近sub-Vth电压方式 约0.2伏，而不是约1.2伏特或更高的超电压状态），并且为了这种操作而进行了优化，特别是通过简化晶体管结构，因为在Vth的工作电压方案中固有的沟道电阻是主要的。 这种简化包括来自栅极的源极和漏极区域的欠叠或凹陷，其避免重叠电容以部分恢复由低电压操作引起的切换速度的损失，厚度为或等于或小于500埃的超薄栅极结构 简化了与晶体管的形成连接，避免了晶体管的源极，漏极和/或栅极中的硅化或合金形成。

公开(公告)号：US20070293031A1

公开(公告)日：2007-12-20

申请号：US11847384

申请日：2007-08-30

申请人： Kevin Chan ,  Jia Chen ,  Shih-Fen Huang ,  Edward Nowak

发明人： Kevin Chan ,  Jia Chen ,  Shih-Fen Huang ,  Edward Nowak

IPC分类号： H01L21/3205

CPC分类号： H01L21/2807 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/665

摘要： A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2 or SixGeyOz interfacial layer of 3 to 4 A thick. The thin SiO2 or SixGeyOz interfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.

摘要翻译： 在栅极电介质上的硅纳米晶种子层上形成场效应晶体管器件的多层栅电极堆叠结构。 硅纳米晶体层的小晶粒尺寸允许使用原位快速热化学气相沉积（RTCVD）沉积高达至少70％的[Ge]的均匀且连续的多晶硅层。 在快速降低的温度下在氧气环境中原位吹扫沉积室导致薄的SiO 2或Si x O x O O 3至4厚的界面层。 薄的SiO 2或Si x Si 2 O 3界面层足够薄且不连续以提供很小的电阻 到栅极电流仍具有足够的[O]以在热处理期间有效地阻挡Ge扩散，从而允许后续沉积的钴的硅化物。 栅电极堆叠结构用于nFET和pFET两者。

公开(公告)号：US20050199906A1

公开(公告)日：2005-09-15

申请号：US11124978

申请日：2005-05-09

申请人： Kevin Chan ,  Jia Chen ,  Shih-Fen Huang ,  Edward Nowak

发明人： Kevin Chan ,  Jia Chen ,  Shih-Fen Huang ,  Edward Nowak

IPC分类号： H01L20060101 ,  H01L21/335 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/24 ,  H01L29/49 ,  H01L29/76 ,  H01L31/072 ,  H01L31/119

CPC分类号： H01L21/2807 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/665

摘要： A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2 or SixGeyOz interfacial layer of 3 to 4 A thick. The thin SiO2 or SixGeyOz interfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.

摘要翻译： 在栅极电介质上的硅纳米晶种子层上形成场效应晶体管器件的多层栅电极堆叠结构。 硅纳米晶体层的小晶粒尺寸允许使用原位快速热化学气相沉积（RTCVD）沉积高达至少70％的[Ge]的均匀且连续的多晶硅层。 在快速降低的温度下在氧气环境中原位吹扫沉积室导致薄的SiO 2或Si x O x O O 3至4厚的界面层。 薄的SiO 2或Si x Si 2 O 3界面层足够薄且不连续以提供很小的电阻 到栅极电流仍具有足够的[O]以在热处理期间有效地阻挡Ge扩散，从而允许后续沉积的钴的硅化物。 栅电极堆叠结构用于nFET和pFET两者。

公开(公告)号：US20050073014A1

公开(公告)日：2005-04-07

申请号：US10680820

申请日：2003-10-07

申请人： Kevin Chan ,  Jia Chen ,  Shih-Fen Huang ,  Edward Nowak

发明人： Kevin Chan ,  Jia Chen ,  Shih-Fen Huang ,  Edward Nowak

IPC分类号： H01L20060101 ,  H01L21/335 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/24 ,  H01L29/49 ,  H01L29/76 ,  H01L31/072 ,  H01L31/119

CPC分类号： H01L21/2807 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/665

摘要： A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2 or SixGeyOz interfacial layer of 3 to 4 A thick. The thin SiO2 or SixGeyOz interfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.

摘要翻译： 在栅极电介质上的硅纳米晶种子层上形成场效应晶体管器件的多层栅电极堆叠结构。 硅纳米晶体层的小晶粒尺寸允许使用原位快速热化学气相沉积（RTCVD）沉积高达至少70％的[Ge]的均匀且连续的多晶硅层。 在快速降低的温度下在氧环境中原位吹扫沉积室导致3至4厚度的薄SiO 2或SixGeyOz界面层。 薄的SiO 2或SixGeyOz界面层是足够薄且不连续的，以提供对栅极电流的很小的阻力，但是具有足够的[O]以在热处理期间有效阻挡向上的Ge扩散，从而允许随后沉积的钴的硅化物。 栅电极堆叠结构用于nFET和pFET两者。

公开(公告)号：US20080057667A1

公开(公告)日：2008-03-06

申请号：US11469940

申请日：2006-09-05

申请人： Huilong Zhu ,  Shih-Fen Huang ,  Effendi Leobandung

发明人： Huilong Zhu ,  Shih-Fen Huang ,  Effendi Leobandung

IPC分类号： H01L21/76

CPC分类号： H01L21/76227 ,  H01L21/823481 ,  H01L22/34

摘要： A test structure for detecting void formation in semiconductor device layers includes a plurality of active device areas formed in a substrate, a plurality of shallow trench isolation (STI) regions separating the active device areas, a plurality of gate electrode structures formed across the active device areas and the STI regions, and a matrix of vias formed over the active device areas and between the gate electrode structures. At least one edge of each of a pair of vias at opposite ends of a given one of the STI regions extends at least out to an edge of the associated active device area.

摘要翻译： 用于检测半导体器件层中的空隙形成的测试结构包括形成在衬底中的多个有源器件区域，分离有源器件区域的多个浅沟槽隔离（STI）区域，跨过有源器件形成的多个栅电极结构 区域和STI区域，以及形成在有源器件区域上和栅电极结构之间的通孔矩阵。 给定一个STI区域的相对端处的一对通孔中的每一个的至少一个边缘至少延伸到相关联的有源器件区域的边缘。

公开(公告)号：US06984564B1

公开(公告)日：2006-01-10

申请号：US10710184

申请日：2004-06-24

申请人： Shih-Fen Huang ,  Clement Wann ,  Haining S. Yang

发明人： Shih-Fen Huang ,  Clement Wann ,  Haining S. Yang

IPC分类号： H01L21/8234 ,  H01L21/8238

CPC分类号： H01L29/7842 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/7843

摘要： An SRAM in a CMOS integrated circuit is subjected to stress on the channels of its transistors; compressive stress on the pull-up and pass gate transistors and tensile stress on the pull-down transistors in a version designed to improve stability; and compressive stress on the pull-up transistors and tensile stress on the pull-down and pass gate transistors in a version designed to reduce the cell size and increase speed of operation.

摘要翻译： CMOS集成电路中的SRAM在其晶体管的沟道上受到应力; 上拉和栅极晶体管中的压应力和下拉晶体管中的拉伸应力，旨在提高稳定性; 并且上拉晶体管中的压应力和下拉和通过栅极晶体管中的拉伸应力在设计成减小电池尺寸并增加操作速度的版本中。

公开(公告)号：US07378336B2

公开(公告)日：2008-05-27

申请号：US11124978

申请日：2005-05-09

申请人： Kevin K. Chan ,  Jia Chen ,  Shih-Fen Huang ,  Edward J. Nowak

发明人： Kevin K. Chan ,  Jia Chen ,  Shih-Fen Huang ,  Edward J. Nowak

IPC分类号： H01L21/3205

CPC分类号： H01L21/2807 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/665

摘要： A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2 or SixGeyOz interfacial layer of 3 to 4 A thick. The thin SiO2 or SixGeyOz interfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.

摘要翻译： 在栅极电介质上的硅纳米晶种子层上形成场效应晶体管器件的多层栅电极堆叠结构。 硅纳米晶体层的小晶粒尺寸允许使用原位快速热化学气相沉积（RTCVD）沉积高达至少70％的[Ge]的均匀且连续的多晶硅层。 在快速降低的温度下在氧气环境中原位吹扫沉积室导致薄的SiO 2或Si x O x O O 3至4厚的界面层。 薄的SiO 2或Si x Si 2 O 3界面层足够薄且不连续以提供很小的电阻 到栅极电流仍具有足够的[O]以在热处理期间有效地阻挡Ge扩散，从而允许后续沉积的钴的硅化物。 栅电极堆叠结构用于nFET和pFET两者。

公开(公告)号：US06975133B1

公开(公告)日：2005-12-13

申请号：US10709784

申请日：2004-05-27

申请人： Victor Wing Chung Chan ,  Hsing-Jen C. Wann ,  Shih-Fen Huang ,  Oleg Gluschenkov

发明人： Victor Wing Chung Chan ,  Hsing-Jen C. Wann ,  Shih-Fen Huang ,  Oleg Gluschenkov

IPC分类号： H01L27/02 ,  H03K17/16 ,  H03K19/017 ,  H03K19/094 ,  H03K19/0948

CPC分类号： H03K19/0948 ,  H01L27/0203 ,  H03K19/01707

摘要： A logic circuit is provided with a first inverter having a plurality of linear gate transistors driving a first capacitive load and a second inverter having a plurality of cellular gate transistors driving a second capacitive load. The first inverter is serially connected to the second inverter. The second capacitive load is larger than the first capacitive load.

摘要翻译： 逻辑电路设置有具有驱动第一电容性负载的多个线性栅极晶体管的第一反相器和驱动第二电容负载的多个蜂窝状栅极晶体管的第二反相器。 第一个逆变器串联连接到第二个逆变器。 第二容性负载大于第一容性负载。

公开(公告)号：US06927454B2

公开(公告)日：2005-08-09

申请号：US10680820

申请日：2003-10-07

申请人： Kevin K. Chan ,  Jia Chen ,  Shih-Fen Huang ,  Edward J. Nowak

发明人： Kevin K. Chan ,  Jia Chen ,  Shih-Fen Huang ,  Edward J. Nowak

IPC分类号： H01L20060101 ,  H01L21/335 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/24 ,  H01L29/49 ,  H01L29/76 ,  H01L31/072 ,  H01L31/119

CPC分类号： H01L21/2807 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/665

摘要： A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2 or SixGeyOz interfacial layer of 3 to 4A thick. The thin SiO2 or SixGeyOz interfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.

摘要翻译： 在栅极电介质上的硅纳米晶种子层上形成场效应晶体管器件的多层栅电极堆叠结构。 硅纳米晶体层的小晶粒尺寸允许使用原位快速热化学气相沉积（RTCVD）沉积高达至少70％的[Ge]的均匀且连续的多晶硅层。 在快速降低的温度下在氧气环境中原位吹扫沉积室导致薄的SiO 2或Si x O x O O 3至4A厚的界面层。 薄的SiO 2或Si x Si 2 O 3界面层足够薄且不连续以提供很小的电阻 到栅极电流仍具有足够的[O]以在热处理期间有效地阻挡Ge扩散，从而允许后续沉积的钴的硅化物。 栅电极堆叠结构用于nFET和pFET两者。