发明申请
US20070132082A1 Copper plating connection for multi-die stack in substrate package
有权
用于多芯片堆叠的基板封装中的镀铜连接
- 专利标题： Copper plating connection for multi-die stack in substrate package
- 专利标题（中）： 用于多芯片堆叠的基板封装中的镀铜连接
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申请号： US11301606申请日： 2005-12-12
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公开(公告)号： US20070132082A1公开(公告)日： 2007-06-14
- 发明人: John Tang , Henry Xu , Jianmin Li , Xiang Zeng
- 申请人： John Tang , Henry Xu , Jianmin Li , Xiang Zeng
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 主分类号： H01L23/12
- IPC分类号： H01L23/12 ; H01L21/58
摘要：
An embodiment of the present invention is a technique to construct a multi-die package. A stack of dice is formed from a base substrate in a package. The dice are positioned one on top of another and have copper plated segments for die interconnection. The dice are interconnected using copper plating to connect the copper plated segments.
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