公开(公告)号：US20070132082A1

公开(公告)日：2007-06-14

申请号：US11301606

申请日：2005-12-12

申请人： John Tang ,  Henry Xu ,  Jianmin Li ,  Xiang Zeng

发明人： John Tang ,  Henry Xu ,  Jianmin Li ,  Xiang Zeng

IPC分类号： H01L23/12 ,  H01L21/58

CPC分类号： H01L23/5383 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/24051 ,  H01L2224/24145 ,  H01L2224/24226 ,  H01L2224/92244 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15165 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/15153

摘要： An embodiment of the present invention is a technique to construct a multi-die package. A stack of dice is formed from a base substrate in a package. The dice are positioned one on top of another and have copper plated segments for die interconnection. The dice are interconnected using copper plating to connect the copper plated segments.

摘要翻译： 本发明的一个实施例是构建多管芯封装的技术。 一堆骰子由包装中的基底形成。 骰子位于另一个的顶部，并具有用于管芯互连的镀铜段。 骰子使用铜电镀互连，以连接镀铜的部分。

公开(公告)号：US20070152312A1

公开(公告)日：2007-07-05

申请号：US11321195

申请日：2005-12-29

申请人： John Tang ,  Xiang Zeng ,  Jiangqi He

发明人： John Tang ,  Xiang Zeng ,  Jiangqi He

IPC分类号： H01L23/12 ,  H01L21/58

CPC分类号： H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/24226 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/30107

摘要： Embodiments of the invention relate to the construction of a dual die package with a high-speed interconnect. A package is created having a first die on a first side of a base substrate and a second die on a second side of the base substrate in opposed relation to the first die. A first copper plated interconnect is plated to the base substrate. Second copper interconnects are formed to connect the first copper plated interconnect to the first and second dice, respectively, such that the first and second dice are interconnected.

摘要翻译： 本发明的实施例涉及具有高速互连的双管芯封装的结构。 制造了在基底基板的第一侧上具有第一模具的封装，和与第一裸片相对的基底基板的第二侧上的第二模具。 第一个镀铜的互连电镀到基底。 形成第二铜互连以将第一镀铜互连件分别连接到第一和第二裸片，使得第一和第二裸片互连。

公开(公告)号：US20070158818A1

公开(公告)日：2007-07-12

申请号：US11323312

申请日：2005-12-30

申请人： John Tang ,  Xiang Zeng ,  Jiangqi He ,  Ding Hai

发明人： John Tang ,  Xiang Zeng ,  Jiangqi He ,  Ding Hai

IPC分类号： H01L23/52

CPC分类号： H01L21/4857 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/85 ,  H01L2224/05553 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/48472 ,  H01L2224/49 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/85 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H05K1/111 ,  H05K1/113 ,  H05K1/162 ,  H05K3/28 ,  H05K2201/0187 ,  H05K2201/09436 ,  H05K2201/09763 ,  H05K2201/10674 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00

摘要： An article includes a top electrode that is embedded in a solder mask. An article includes a top electrode that is on a core structure. A process of forming the top electrode includes reducing the solder mask thickness and forming the top electrode on the reduced-thickness solder mask. A process of forming the top electrode includes forming the top electrode over a high-K dielectric that is in a patterned portion of the core structure.

摘要翻译： 一种物品包括埋在焊接掩模中的顶部电极。 一种物品包括在核心结构上的顶部电极。 形成顶部电极的工艺包括减小焊接掩模厚度并在厚度较薄的焊接掩模上形成顶部电极。 形成顶部电极的工艺包括在位于芯结构的图案化部分中的高K电介质上形成顶部电极。

公开(公告)号：US20150035603A1

公开(公告)日：2015-02-05

申请号：US14380465

申请日：2012-02-24

申请人： Xiang Zeng ,  Changjiang Yang ,  Tao Huang

发明人： Xiang Zeng ,  Changjiang Yang ,  Tao Huang

IPC分类号： H03F1/32 ,  H03F3/19 ,  H03F3/21

CPC分类号： H03F1/3223 ,  H03F1/3229 ,  H03F3/19 ,  H03F3/211 ,  H03F3/24 ,  H03F2200/336 ,  H03F2200/451 ,  H03F2203/21142

摘要： The present application discloses a feed-forward amplifier device and the method thereof. The device comprises: a splitter for splitting an input signal into two portions; a non-linear amplifier for amplifying the input signal and producing inter-modulation products; a carrier canceling unit for generating pure inter-modulation products; a linear amplifier for amplifying the pure inter-modulation products; and a coupler for generating final output signal by counteracting the inter-modulation products with the amplified pure inter-modulation products; wherein the splitter and the carrier canceling unit are provided in digital base band. According to the present disclosure, pure inter-modulation products can be generated and adjusted more flexibly and more accurately in digital base band, and hence ideal output signal may be generated.

摘要翻译： 本申请公开了一种前馈放大器装置及其方法。 该装置包括：分离器，用于将输入信号分成两部分; 用于放大输入信号并产生互调产物的非线性放大器; 用于产生纯互调产物的载波消除单元; 用于放大纯互调制品的线性放大器; 以及耦合器，用于通过将所述互调产物与所述放大纯互调产物相抵消来产生最终输出信号; 其中分离器和载波消除单元设置在数字基带中。 根据本公开，可以在数字基带中更灵活，更准确地生成和调整纯互调制品，因此可以产生理想的输出信号。

公开(公告)号：US20070146105A1

公开(公告)日：2007-06-28

申请号：US11320942

申请日：2005-12-28

申请人： Xiang Zeng ,  Jiangqi He ,  BaoShu Xu

发明人： Xiang Zeng ,  Jiangqi He ,  BaoShu Xu

IPC分类号： H01F1/00

CPC分类号： H01F17/0006 ,  H01F27/346 ,  H01F27/38 ,  H01F2017/0046 ,  H01F2017/0073 ,  H01F2017/008

摘要： Complementary inductor structures. The inductor structure may include two or more sub-inductors that have positive coupling to provide a total inductance approximately equal to the sum of the inductance provided by the two or more sub-inductors. Radiation from the two or more sub-inductors may be in different phases to partially, or even totally, cancel and result in a reduced overall radiation, which may reduce electromagnetic interference and/or electromagnetic coupling.

摘要翻译： 互补电感结构。 电感器结构可以包括具有正耦合的两个或更多个子电感器，以提供大致等于由两个或多个子电感器提供的电感之和的总电感。 来自两个或更多个子电感器的辐射可以处于不同的相位以部分或甚至完全消除并导致减小的总辐射，这可以减少电磁干扰和/或电磁耦合。

公开(公告)号：US20070102733A1

公开(公告)日：2007-05-10

申请号：US11270271

申请日：2005-11-09

申请人： Qing Zhou ,  Daoqiang Lu ,  Jiangqi He ,  Wei Shi ,  Xiang Zeng

发明人： Qing Zhou ,  Daoqiang Lu ,  Jiangqi He ,  Wei Shi ,  Xiang Zeng

IPC分类号： H01L29/768

CPC分类号： H01L23/48 ,  H01L25/0652 ,  H01L2924/00014 ,  H01L2224/48

摘要： Disclosed are embodiments of a multi-chip assembly including optically coupled die. The multi-chip assembly may include two opposing substrates, and a number of die are mounted on each of the substrates. At least one die on one of the substrates is in optical communication with at least one opposing die on the other substrate. Other embodiments are described and claimed.

摘要翻译： 公开了包括光耦合管芯的多芯片组件的实施例。 多芯片组件可以包括两个相对的基板，并且在每个基板上安装多个管芯。 一个基板上的至少一个管芯与另一个基板上的至少一个相对的管芯光学连通。 描述和要求保护其他实施例。

公开(公告)号：US20070155195A1

公开(公告)日：2007-07-05

申请号：US11324040

申请日：2005-12-30

申请人： Jiangqi He ,  BaoShu Xu ,  Xiang Zeng

发明人： Jiangqi He ,  BaoShu Xu ,  Xiang Zeng

IPC分类号： H01R12/00

CPC分类号： H01R13/6461 ,  H01R13/6477 ,  Y10S439/941

摘要： Data signal interconnections are described that offer reduced cross talk particularly with high speed differential signaling. In one example, the invention includes a plurality of interconnects to carry data signals between a first component and a second component, the plurality of interconnects including a first set of interconnects oriented in a first direction and a second set of interconnects oriented in a second direction, different from the first direction

摘要翻译： 描述了数据信号互连，其提供减少的串扰，特别是与高速差分信号。 在一个示例中，本发明包括在第一组件和第二组件之间承载数据信号的多个互连，所述多个互连包括在第一方向上定向的第一组互连和在第二方向上定向的第二组互连 ，不同于第一个方向

公开(公告)号：US20070152796A1

公开(公告)日：2007-07-05

申请号：US11323339

申请日：2005-12-30

申请人： Jiangqi He ,  Robert Sankman ,  BaoShu Xu ,  Xiang Zeng

发明人： Jiangqi He ,  Robert Sankman ,  BaoShu Xu ,  Xiang Zeng

IPC分类号： H01F27/28

CPC分类号： H01F17/0006 ,  H01F27/323 ,  H01F41/041 ,  H01F2017/0046 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

摘要： A spiral inductor is disposed above a substrate that includes two different materials. A dielectric film is the first material that provides structural integrity for the substrate. A second dielectric is the second material that provides a low dielectric-constant (low-K) material closest to the spiral inductor coil. A process of forming the spiral inductor includes patterning the substrate to allow a recess as a receptacle for the second dielectric, followed by forming the spiral inductor mostly above the second dielectric.

摘要翻译： 螺旋电感器设置在包括两种不同材料的衬底之上。 电介质膜是为衬底提供结构完整性的第一种材料。 第二介质是提供最接近螺旋电感线圈的低介电常数（低K）材料的第二材料。 形成螺旋电感器的过程包括图案化衬底以允许凹槽作为用于第二电介质的插座，随后形成主要位于第二电介质上方的螺旋电感器。

公开(公告)号：US20060180905A1

公开(公告)日：2006-08-17

申请号：US11060104

申请日：2005-02-16

申请人： Xiang Zeng ,  Jiangqi He ,  BaoShu Xu

发明人： Xiang Zeng ,  Jiangqi He ,  BaoShu Xu

IPC分类号： H01L23/02 ,  H01L23/12 ,  H01L23/34

CPC分类号： H01L23/49822 ,  H01L23/50 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15313

摘要： In one embodiment, an integrated circuit package comprises a substrate including a first surface having a plurality of signal land pads and a second surface having a plurality of signal die pads; a plurality of signal connectors arranged to electrically couple the plurality of the signal land pads to the plurality of the signal die pads; and a ground plane, disposed in an adjacent, spaced-apart relationship to the plurality of signal land pads. The ground plane includes a plurality of holes with at least one of the holes having at least one of the signal connectors extending therethrough and being dimensioned and configured approximately to be as large or larger than at least one of the signal land pads disposed adjacent to the at least one hole.

摘要翻译： 在一个实施例中，集成电路封装包括：衬底，其包括具有多个信号焊盘的第一表面和具有多个信号管芯焊盘的第二表面; 多个信号连接器，其布置成将多个信号焊盘区电耦合到多个信号管芯焊盘; 以及接地平面，与多个信号焊盘相邻设置成间隔开的关系。 接地平面包括多个孔，其中至少一个孔具有延伸穿过其中的信号连接器中的至少一个，其尺寸和构造近似大于或大于与邻近 至少有一个洞。

公开(公告)号：US08598465B2

公开(公告)日：2013-12-03

申请号：US13015132

申请日：2011-01-27

申请人： David M. Eaves ,  Xiang Zeng ,  Kelly J. Hennig ,  Patty Pei-Ling Chang-Chien

发明人： David M. Eaves ,  Xiang Zeng ,  Kelly J. Hennig ,  Patty Pei-Ling Chang-Chien

IPC分类号： H05K1/11

CPC分类号： H01L23/522 ,  H01L21/50 ,  H01L21/561 ,  H01L23/10 ,  H01L23/5329 ,  H01L23/552 ,  H01L23/585 ,  H01L23/66 ,  H01L24/80 ,  H01L25/0657 ,  H01L2223/6683 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06537 ,  H01L2224/80

摘要： A wafer-scale assembly circuit including a plurality of metal interconnect layers, where each metal layer includes patterned metal portions and where at least some of the patterned metal portions are RF signal lines. The circuit further includes at least one benzocyclobutene layer provided between two metal interconnect layers that includes at least one trench via formed around a perimeter of the benzocyclobutene layer at a circuit sealing ring, where the trench via provides a hermetic seal at the sealing ring. The benzocyclobutene layer also includes a plurality of stabilizing post vias formed through the benzocyclobutene layer adjacent to the trench via proximate to the sealing ring and extending around the perimeter of the benzocyclobutene layer, where the stabilizing vias operate to prevent the benzocyclobutene layer from shrinking in size.

摘要翻译： 包括多个金属互连层的晶片级组装电路，其中每个金属层包括图案化的金属部分，并且其中至少一些图案化的金属部分是RF信号线。 该电路还包括至少一个设置在两个金属互连层之间的苯并环丁烯层，其包括在电路密封环处围绕苯并环丁烯层的周边形成的至少一个沟槽通道，其中沟槽通孔在密封环处提供气密密封。 苯并环丁烯层还包括多个稳定的通孔，其通过邻近密封环的邻近沟槽的苯并环丁烯层形成，并且围绕苯并环丁烯层的周边延伸，其中稳定通孔的作用是防止苯并环丁烯层的尺寸收缩 。