发明申请
- 专利标题: Method of fabricating semiconductor integrated circuit device
- 专利标题(中): 制造半导体集成电路器件的方法
-
申请号: US11783187申请日: 2007-04-06
-
公开(公告)号: US20070184603A1公开(公告)日: 2007-08-09
- 发明人: Shinji Nishihara , Shuji Ikeda , Naotaka Hashimoto , Hiroshi Momiji , Hiromi Abe , Shinichi Fukada , Masayuki Suzuki
- 申请人: Shinji Nishihara , Shuji Ikeda , Naotaka Hashimoto , Hiroshi Momiji , Hiromi Abe , Shinichi Fukada , Masayuki Suzuki
- 主分类号: H01L21/8238
- IPC分类号: H01L21/8238
摘要:
A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.