The RF power amplifier includes first and second amplifiers Q1 and Q2 as final-stage amplification power devices connected in parallel between an input terminal RF_In and an output terminal RF_Out. The amplifiers Q1 and Q2 are formed on one semiconductor chip. The first bias voltage Vg1 of the amplifier Q1 is set to be higher than the second bias voltage Vg2 of the amplifier Q2 so that the amplifier Q1 is operational between Class B and AB, and Q2 is operational in Class C. The first effective device size Wgq1 of the amplifier Q1 is intentionally set to be smaller than the second effective device size Wgq2 of the amplifier Q2 beyond a range of a manufacturing error of the semiconductor chip. An RF power amplifier that exhibits a high power-added efficiency characteristic regardless of whether the output power is High or Low can be materialized.