- 专利标题: Method for designing phase-lock loop circuits
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申请号: US11472199申请日: 2006-06-20
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公开(公告)号: US20080007348A1公开(公告)日: 2008-01-10
- 发明人: Mu-Jen Huang , Chien-Hung Chen , Chih-Chiang Chang
- 申请人: Mu-Jen Huang , Chien-Hung Chen , Chih-Chiang Chang
- 专利权人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 主分类号: H03L7/00
- IPC分类号: H03L7/00
摘要:
A method for designing a phase-lock loop (PLL) circuit is disclosed. The method includes the following steps. A first set of intellectual properties, each of which represents a control circuit implemented on a semiconductor substrate, is provided. A second set of intellectual properties, each of which represents a filter implemented on the semiconductor substrate, is provided. Intellectual properties are selected from the first and second sets based on a predetermined specification of the PLL circuit. The selected intellectual properties are integrated as an integrated intellectual property representing the PLL circuit, such that a layout area of the PLL circuit implemented by using the integrated intellectual property is configured based on the predetermined specification.
公开/授权文献
- US07464346B2 Method for designing phase-lock loop circuits 公开/授权日:2008-12-09