公开(公告)号：US20130326447A1

公开(公告)日：2013-12-05

申请号：US13484480

申请日：2012-05-31

申请人： Mu-Jen HUANG ,  Yu-Sian JIANG ,  Yi-Ting LIN ,  Hsien-Yu TSENG ,  Heng Kai LIU ,  Chien-Wen CHEN ,  Chauchin SU

发明人： Mu-Jen HUANG ,  Yu-Sian JIANG ,  Yi-Ting LIN ,  Hsien-Yu TSENG ,  Heng Kai LIU ,  Chien-Wen CHEN ,  Chauchin SU

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/82

摘要： A system comprises an electronic design automation (EDA) tool, for generating a schematic design of an integrated circuit (IC), generating a layout from the schematic design, editing the layout, and verifying the schematic design and layout. At least one non-transitory, computer readable storage medium, is provided for storing data representing the schematic design and the layout, the layout having a network of routing paths connecting at least two active layer devices of the IC design. An RC tool is provided for computing estimated parasitic capacitances of the routing paths of the network before verifying the schematic design and layout, and for inserting a capacitor corresponding to the estimated parasitic capacitance into the data representing the schematic design of the IC. A first device level simulation tool for simulating performance of the network based on the at least two active layer devices and the estimated parasitic capacitances.

摘要翻译： 一种系统包括电子设计自动化（EDA）工具，用于产生集成电路（IC）的示意性设计，从原理图设计生成布局，编辑布局以及验证原理图设计和布局。 提供了至少一个非暂时的计算机可读存储介质，用于存储表示示意图设计和布局的数据，该布局具有连接IC设计的至少两个有源层设备的路由路径网络。 提供了一种RC工具，用于在验证原理图设计和布局之前计算网络路由路径的估计寄生电容，并将与估计的寄生电容对应的电容插入到表示IC原理图设计的数据中。 用于基于至少两个有源层器件和估计的寄生电容来模拟网络的性能的第一器件级仿真工具。

公开(公告)号：US20080106345A1

公开(公告)日：2008-05-08

申请号：US11592453

申请日：2006-11-03

申请人： Mu-Jen Huang

发明人： Mu-Jen Huang

IPC分类号： H03K3/03

CPC分类号： H03K3/0315 ,  H03K5/133 ,  H03K2005/00032 ,  H03L7/0995 ,  H03L7/10

摘要： A voltage controlled oscillator includes at least one input port for receiving a control voltage and at least one voltage-to-current coupled to the input port for generating a control current in response to the control voltage. At least one current controlled oscillator generates an oscillating frequency output in response to the control current. At least one compensation branch is coupled to the voltage-to-current converter for generating a compensation current that increases the control current when the control voltage exceeds a predetermined value.

摘要翻译： 压控振荡器包括用于接收控制电压的至少一个输入端口和耦合到输入端口的至少一个电压 - 电流，用于响应于控制电压产生控制电流。 至少一个电流控制振荡器响应于控制电流产生振荡频率输出。 至少一个补偿分支耦合到电压 - 电流转换器，用于产生当控制电压超过预定值时增加控制电流的补偿电流。

公开(公告)号：US20200218347A1

公开(公告)日：2020-07-09

申请号：US16735693

申请日：2020-01-06

申请人： Yu-Sian Jiang ,  Mu-Jen Huang

发明人： Yu-Sian Jiang ,  Mu-Jen Huang

IPC分类号： G06F3/01 ,  G06K9/00 ,  G02B27/01 ,  G02B27/00

摘要： A control system is provided. The control system includes an image capturing unit, an input interface and a processing unit. The image capturing unit is configured to capture a plurality of images of a user. The input interface configured to receive an input signal from the user. The processing unit is configured to identify a facial feature from the captured images; calculate a gaze point of the user according to the facial feature; determine a target facility among multiple facilities according to the gaze point of the user; receive a confirmation signal; configure the target facility as a facility subject to control when the confirmation signal is received; and control the facility subject to control in response to a control signal received from the input interface.

公开(公告)号：US07464346B2

公开(公告)日：2008-12-09

申请号：US11472199

申请日：2006-06-20

申请人： Mu-Jen Huang ,  Chien-Hung Chen ,  Chih-Chiang Chang

发明人： Mu-Jen Huang ,  Chien-Hung Chen ,  Chih-Chiang Chang

IPC分类号： G06F17/50

CPC分类号： H03L7/00

摘要： A method for designing a phase-lock loop (PLL) circuit is disclosed. The method includes the following steps. A first set of intellectual properties, each of which represents a control circuit implemented on a semiconductor substrate, is provided. A second set of intellectual properties, each of which represents a filter implemented on the semiconductor substrate, is provided. Intellectual properties are selected from the first and second sets based on a predetermined specification of the PLL circuit. The selected intellectual properties are integrated as an integrated intellectual property representing the PLL circuit, such that a layout area of the PLL circuit implemented by using the integrated intellectual property is configured based on the predetermined specification.

摘要翻译： 公开了一种用于设计锁相环（PLL）电路的方法。 该方法包括以下步骤。 提供了第一组知识产权，其中每个都代表在半导体衬底上实现的控制电路。 提供了第二组知识产权，其中每一个代表在半导体衬底上实现的滤波器。 基于PLL电路的预定规格，从第一和第二组中选择智能属性。 所选择的知识产权被集成为代表PLL电路的综合知识产权，使得基于预定规范配置通过使用集成知识产权实现的PLL电路的布局区域。

公开(公告)号：US20080007348A1

公开(公告)日：2008-01-10

申请号：US11472199

申请日：2006-06-20

申请人： Mu-Jen Huang ,  Chien-Hung Chen ,  Chih-Chiang Chang

发明人： Mu-Jen Huang ,  Chien-Hung Chen ,  Chih-Chiang Chang

IPC分类号： H03L7/00

CPC分类号： H03L7/00

摘要： A method for designing a phase-lock loop (PLL) circuit is disclosed. The method includes the following steps. A first set of intellectual properties, each of which represents a control circuit implemented on a semiconductor substrate, is provided. A second set of intellectual properties, each of which represents a filter implemented on the semiconductor substrate, is provided. Intellectual properties are selected from the first and second sets based on a predetermined specification of the PLL circuit. The selected intellectual properties are integrated as an integrated intellectual property representing the PLL circuit, such that a layout area of the PLL circuit implemented by using the integrated intellectual property is configured based on the predetermined specification.

公开(公告)号：US07113560B1

公开(公告)日：2006-09-26

申请号：US10253293

申请日：2002-09-24

申请人： Mu-Jen Huang ,  Linhsiang Wei ,  Fu-Shing Ju

发明人： Mu-Jen Huang ,  Linhsiang Wei ,  Fu-Shing Ju

IPC分类号： H04L7/00

CPC分类号： H04L7/0338

摘要： A method and circuit to produce an optimal sampling phase for recovery of a digital signal is achieved. A digital signal is over-sampled by sampling on each phase of a multiple phase clock to generate a sample value per phase. The multiple phase clock may be generated by a DLL. A voted value is determined per phase comprising a majority value of a set of consecutive sample values. Transition phases are sensed. A transition phase is defined as two consecutive voted phases comprising different values. The transition phases are compared to a stored phase state to determine a signal shift direction. The signal shift direction is filtered to generate a state update signal. The stored phase state is updated based on the state update signal. The stored phase state corresponds to an optimal sampling phase for recovery of the digital signal.

摘要翻译： 实现了用于产生用于恢复数字信号的最佳采样相位的方法和电路。 数字信号通过对多相时钟的每相进行采样而被过采样，以产生每相的采样值。 多相时钟可以由DLL生成。 每个阶段确定包括一组连续样本值的多数值的投票值。 检测过渡阶段。 过渡阶段被定义为包括不同值的两个连续投票阶段。 将过渡阶段与存储的相位状态进行比较以确定信号偏移方向。 信号移位方向被滤波以产生状态更新信号。 基于状态更新信号来更新存储的相位状态。 存储的相位状态对应于用于恢复数字信号的最佳采样相位。

公开(公告)号：US11272086B2

公开(公告)日：2022-03-08

申请号：US16737897

申请日：2020-01-08

申请人： Yu-Sian Jiang ,  Mu-Jen Huang

发明人： Yu-Sian Jiang ,  Mu-Jen Huang

IPC分类号： H04N5/225 ,  H04N5/232 ,  G02B27/01 ,  B60K35/00 ,  B60R11/04

摘要： A camera system is provided. The camera system includes an image sensor, at least one light source, and a processing unit. The image sensor is configured to capture a plurality of images. The processing unit is configured to perform the following instructions. A plurality of reflection values on at least one subject in the captured images is acquired. A relationship between a luminance level of the light sources and a reflection level on the at least one subject is obtained. A luminance configuration is determined according to the relationship between the luminance level of the light sources and the reflection level on the at least one subject. A luminous power of at least one of the light sources is adjusted according to the luminance configuration.

公开(公告)号：US08904326B2

公开(公告)日：2014-12-02

申请号：US13539258

申请日：2012-06-29

申请人： Mu-Jen Huang ,  Chih Chi Hsiao ,  Wei-Ting Lin ,  Tsung-Hsin Yu ,  Chien-Wen Chen ,  Yung-Chow Peng

发明人： Mu-Jen Huang ,  Chih Chi Hsiao ,  Wei-Ting Lin ,  Tsung-Hsin Yu ,  Chien-Wen Chen ,  Yung-Chow Peng

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/505 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081

摘要： In a semiconductor device design method performed by at least one processor, location data of at least one electrical component in a layout of a semiconductor device is extracted by the at least one processor. Voltage data associated with the at least one electrical component and based on a simulation of an operation of the semiconductor device is extracted by the at least one processor. Based on the extracted location data, the extracted voltage data is incorporated, by the at least one processor, in the layout to generate a modified layout of the semiconductor device.

摘要翻译： 在由至少一个处理器执行的半导体器件设计方法中，所述至少一个处理器提取半导体器件的布局中的至少一个电气部件的位置数据。 由至少一个处理器提取与所述至少一个电气部件相关联并且基于所述半导体器件的操作的模拟的电压数据。 基于所提取的位置数据，所提取的电压数据由所述至少一个处理器并入所述布局中以生成所述半导体器件的修改的布局。

公开(公告)号：US08806414B2

公开(公告)日：2014-08-12

申请号：US13484480

申请日：2012-05-31

申请人： Mu-Jen Huang ,  Yu-Sian Jiang ,  Yi-Ting Lin ,  Hsien-Yu Tseng ,  Heng Kai Liu ,  Chien-Wen Chen ,  Chauchin Su

发明人： Mu-Jen Huang ,  Yu-Sian Jiang ,  Yi-Ting Lin ,  Hsien-Yu Tseng ,  Heng Kai Liu ,  Chien-Wen Chen ,  Chauchin Su

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/82

摘要： A system comprises an electronic design automation (EDA) tool, for generating a schematic design of an integrated circuit (IC), generating a layout from the schematic design, editing the layout, and verifying the schematic design and layout. At least one non-transitory, computer readable storage medium, is provided for storing data representing the schematic design and the layout, the layout having a network of routing paths connecting at least two active layer devices of the IC design. An RC tool is provided for computing estimated parasitic capacitances of the routing paths of the network before verifying the schematic design and layout, and for inserting a capacitor corresponding to the estimated parasitic capacitance into the data representing the schematic design of the IC. A first device level simulation tool for simulating performance of the network based on the at least two active layer devices and the estimated parasitic capacitances.

摘要翻译： 一种系统包括电子设计自动化（EDA）工具，用于产生集成电路（IC）的示意性设计，从原理图设计生成布局，编辑布局以及验证原理图设计和布局。 提供了至少一个非暂时的计算机可读存储介质，用于存储表示示意图设计和布局的数据，该布局具有连接IC设计的至少两个有源层设备的路由路径网络。 提供了一种RC工具，用于在验证原理图设计和布局之前计算网络路由路径的估计寄生电容，并将与估计的寄生电容对应的电容插入到表示IC原理图设计的数据中。 用于基于至少两个有源层器件和估计的寄生电容来模拟网络的性能的第一器件级仿真工具。

公开(公告)号：US08775993B2

公开(公告)日：2014-07-08

申请号：US13601773

申请日：2012-08-31

申请人： Mu-Jen Huang ,  Yu-Sian Jiang ,  Chien-Wen Chen

发明人： Mu-Jen Huang ,  Yu-Sian Jiang ,  Chien-Wen Chen

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/5009 ,  G06F17/5081

摘要： A design system for designing an integrated circuit that includes a processor, a memory coupled to the processor, and instructions to generate and edit a schematic of the integrated circuit, generate at least one recommended layout parameter of an integrated circuit device within the integrated circuit, extract the at least one recommended layout parameter during a layout stage of the integrated circuit, and calculate a circuit performance parameter of the integrated circuit using the at least one recommended layout parameter, and a user interface configured to display at least one of the circuit performance parameter and layout constraints of the integrated circuit device of the integrated circuit.

摘要翻译： 一种用于设计包括处理器，耦合到处理器的存储器和用于生成和编辑集成电路的原理图的指令的集成电路的设计系统，生成集成电路内的集成电路器件的至少一个推荐布局参数， 在所述集成电路的布局阶段期间提取所述至少一个推荐的布局参数，以及使用所述至少一个推荐布局参数来计算所述集成电路的电路性能参数;以及用户界面，被配置为显示所述电路性能中的至少一个 集成电路集成电路器件的参数和布局约束。