发明申请
US20080042207A1 Contact array layout for improving ESD capability of CMOS transistors
审中-公开
接触阵列布局,以改善CMOS晶体管的ESD能力
- 专利标题: Contact array layout for improving ESD capability of CMOS transistors
- 专利标题(中): 接触阵列布局,以改善CMOS晶体管的ESD能力
-
申请号: US11506948申请日: 2006-08-17
-
公开(公告)号: US20080042207A1公开(公告)日: 2008-02-21
- 发明人: Yi-Hsun Wu , Jian-Hsing Lee , Kuo-Feng Yu , C.S. Tang , Cheng-Chun Ting
- 申请人: Yi-Hsun Wu , Jian-Hsing Lee , Kuo-Feng Yu , C.S. Tang , Cheng-Chun Ting
- 专利权人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 主分类号: H01L23/62
- IPC分类号: H01L23/62
摘要:
A transistor layout is disclosed for improving electrostatic discharge capabilities. The layout has a first gate region with a first active region and a second active region formed on two sides thereof, and a second gate region placed next to the second active region with a third active region placed on an opposing side of the second gate region from the second active region. A first and a second set of contacts formed on the first and the third active regions, and a third set of contacts formed on the second active region, wherein the third set of contacts are spaced in parallel with and offset from the other two sets of contacts such that no contact from the third set is aligned laterally with a contact from either the first or the second set of contacts.
信息查询
IPC分类: