Contact array layout for improving ESD capability of CMOS transistors
    1.
    发明申请
    Contact array layout for improving ESD capability of CMOS transistors 审中-公开
    接触阵列布局,以改善CMOS晶体管的ESD能力

    公开(公告)号:US20080042207A1

    公开(公告)日:2008-02-21

    申请号:US11506948

    申请日:2006-08-17

    IPC分类号: H01L23/62

    摘要: A transistor layout is disclosed for improving electrostatic discharge capabilities. The layout has a first gate region with a first active region and a second active region formed on two sides thereof, and a second gate region placed next to the second active region with a third active region placed on an opposing side of the second gate region from the second active region. A first and a second set of contacts formed on the first and the third active regions, and a third set of contacts formed on the second active region, wherein the third set of contacts are spaced in parallel with and offset from the other two sets of contacts such that no contact from the third set is aligned laterally with a contact from either the first or the second set of contacts.

    摘要翻译: 公开了用于改善静电放电能力的晶体管布局。 布局具有第一栅极区域,其具有形成在其两侧的第一有源区和第二有源区,以及放置在第二有源区旁边的第二栅极区,第三有源区位于第二栅极区的相对侧 从第二个活跃区域。 形成在第一和第三有源区上的第一和第二组触点,以及形成在第二有源区上的第三组触点,其中第三组触点与另外两组触点间隔开并偏离 触点,使得第三组的接触不与来自第一组或第二组触点的触点对齐。