公开(公告)号：US20060289935A1

公开(公告)日：2006-12-28

申请号：US11512850

申请日：2006-08-29

申请人： Kuo-Feng Yu ,  Jian-Hsing Lee ,  Yi-Hsun Wu ,  C.S Tang

发明人： Kuo-Feng Yu ,  Jian-Hsing Lee ,  Yi-Hsun Wu ,  C.S Tang

IPC分类号： H01L23/62

CPC分类号： H01L27/0266

摘要： A layout structure for an ESD protection circuit includes a first MOS device area having a first and second doped regions of the same polarity disposed at two sides of a first conductive gate layer, and a third doped region disposed along the first doped region at one side of the first conductive gate layer. The third doped region has a polarity different from that of the first and second doped regions, such that the third doped region and the second doped region form a diode for enhancing dissipation of ESD current during a negative ESD event.

摘要翻译： ESD保护电路的布局结构包括：第一MOS器件区域，具有设置在第一导电栅极层的两侧的具有相同极性的第一和第二掺杂区域;以及第三掺杂区域，沿第一掺杂区域设置在一侧 的第一导电栅极层。 第三掺杂区域具有与第一和第二掺杂区域不同的极性，使得第三掺杂区域和第二掺杂区域形成用于在负ESD事件期间增强ESD电流的耗散的二极管。

公开(公告)号：US07465994B2

公开(公告)日：2008-12-16

申请号：US11512850

申请日：2006-08-29

申请人： Kuo-Feng Yu ,  Jian-Hsing Lee ,  Yi-Hsun Wu ,  C.S Tang

发明人： Kuo-Feng Yu ,  Jian-Hsing Lee ,  Yi-Hsun Wu ,  C.S Tang

IPC分类号： H01L23/62

CPC分类号： H01L27/0266

摘要： A layout structure for an ESD protection circuit includes a first MOS device area having a first and second doped regions of the same polarity disposed at two sides of a first conductive gate layer, and a third doped region disposed along the first doped region at one side of the first conductive gate layer. The third doped region has a polarity different from that of the first and second doped regions, such that the third doped region and the second doped region form a diode for enhancing dissipation of ESD current during a negative ESD event.

摘要翻译： ESD保护电路的布局结构包括：第一MOS器件区域，具有设置在第一导电栅极层的两侧的具有相同极性的第一和第二掺杂区域;以及第三掺杂区域，沿第一掺杂区域设置在一侧 的第一导电栅极层。 第三掺杂区域具有与第一和第二掺杂区域不同的极性，使得第三掺杂区域和第二掺杂区域形成用于在负ESD事件期间增强ESD电流的耗散的二极管。

公开(公告)号：US20080042207A1

公开(公告)日：2008-02-21

申请号：US11506948

申请日：2006-08-17

申请人： Yi-Hsun Wu ,  Jian-Hsing Lee ,  Kuo-Feng Yu ,  C.S. Tang ,  Cheng-Chun Ting

发明人： Yi-Hsun Wu ,  Jian-Hsing Lee ,  Kuo-Feng Yu ,  C.S. Tang ,  Cheng-Chun Ting

IPC分类号： H01L23/62

CPC分类号： H01L23/60 ,  H01L24/06 ,  H01L27/0207 ,  H01L27/0266 ,  H01L29/41775 ,  H01L29/4238 ,  H01L2224/0401 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

摘要： A transistor layout is disclosed for improving electrostatic discharge capabilities. The layout has a first gate region with a first active region and a second active region formed on two sides thereof, and a second gate region placed next to the second active region with a third active region placed on an opposing side of the second gate region from the second active region. A first and a second set of contacts formed on the first and the third active regions, and a third set of contacts formed on the second active region, wherein the third set of contacts are spaced in parallel with and offset from the other two sets of contacts such that no contact from the third set is aligned laterally with a contact from either the first or the second set of contacts.

摘要翻译： 公开了用于改善静电放电能力的晶体管布局。 布局具有第一栅极区域，其具有形成在其两侧的第一有源区和第二有源区，以及放置在第二有源区旁边的第二栅极区，第三有源区位于第二栅极区的相对侧 从第二个活跃区域。 形成在第一和第三有源区上的第一和第二组触点，以及形成在第二有源区上的第三组触点，其中第三组触点与另外两组触点间隔开并偏离 触点，使得第三组的接触不与来自第一组或第二组触点的触点对齐。