发明申请
- 专利标题: DIGITAL PHASE LOCKED LOOP
- 专利标题(中): 数字相位锁定环
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申请号: US11939894申请日: 2007-11-14
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公开(公告)号: US20080116982A1公开(公告)日: 2008-05-22
- 发明人: Robertus Laurentius van der Valk , Paulus Hendricus Lodewijk Maria Schram , Johannes Hermanus Aloysius de Rijk
- 申请人: Robertus Laurentius van der Valk , Paulus Hendricus Lodewijk Maria Schram , Johannes Hermanus Aloysius de Rijk
- 申请人地址: CA Kanata
- 专利权人: ZARLINK SEMICONDUCTOR INC.
- 当前专利权人: ZARLINK SEMICONDUCTOR INC.
- 当前专利权人地址: CA Kanata
- 优先权: GB0622948.8 20061117
- 主分类号: H03L7/085
- IPC分类号: H03L7/085 ; H03L7/08
摘要:
A digital phase locked loop includes a phase acquisition unit for producing a digital representation of the phase of a reference signal, a digital phase detector having a first input receiving a digital signal from, or derived from, the output of the phase acquisition unit, digital loop filter filtering the output of the digital phase detector, and a digital controlled oscillator generating an output signal under the control of the digital loop filter. A digital feedback loop provides a second input to the digital phase detector from the output of the digital controlled oscillator.
公开/授权文献
- US07642862B2 Digital phase locked loop 公开/授权日:2010-01-05
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