- 专利标题: DESIGN PATTERN CORRECTING METHOD, DESIGN PATTERN FORMING METHOD, PROCESS PROXIMITY EFFECT CORRECTING METHOD, SEMICONDUCTOR DEVICE AND DESIGN PATTERN CORRECTING PROGRAM
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申请号: US12269705申请日: 2008-11-12
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公开(公告)号: US20090077530A1公开(公告)日: 2009-03-19
- 发明人: TOSHIYA KOTANI , Shigeki Nojima , Shimon Maeda
- 申请人: TOSHIYA KOTANI , Shigeki Nojima , Shimon Maeda
- 申请人地址: JP Tokyo
- 专利权人: KABUSHIKI KAISHA TOSHIBA
- 当前专利权人: KABUSHIKI KAISHA TOSHIBA
- 当前专利权人地址: JP Tokyo
- 优先权: JP2004-134011 20040428
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
A design pattern correcting method of correcting a design pattern in relation to a minute step of the design pattern, is disclosed, which comprises extracting at least one of two edges extended from a vertex of the design pattern, measuring a length of the extracted edge, determining whether or not the length of the measured edge is shorter than a predetermined value, extracting two vertexes connected to the extracted edge if it is determined that the length of the extracted edge is shorter than the predetermined value, and reshaping the design pattern to match positions of the two extracted vertexes with each other.
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