公开(公告)号：US20050251781A1

公开(公告)日：2005-11-10

申请号：US11115322

申请日：2005-04-27

申请人： Toshiya Kotani ,  Shigeki Nojima ,  Shimon Maeda

发明人： Toshiya Kotani ,  Shigeki Nojima ,  Shimon Maeda

IPC分类号： G03C5/00 ,  G03F1/36 ,  G03F1/68 ,  G03F9/00 ,  G06F17/50 ,  H01L21/027

CPC分类号： G03F1/36

摘要： A design pattern correcting method of correcting a design pattern in relation to a minute step of the design pattern, is disclosed, which comprises extracting at least one of two edges extended from a vertex of the design pattern, measuring a length of the extracted edge, determining whether or not the length of the measured edge is shorter than a predetermined value, extracting two vertexes connected to the extracted edge if it is determined that the length of the extracted edge is shorter than the predetermined value, and reshaping the design pattern to match positions of the two extracted vertexes with each other.

摘要翻译： 公开了一种相对于设计图案的微小步骤校正设计图案的设计图案校正方法，其包括提取从设计图案的顶点延伸的两个边缘中的至少一个，测量提取的边缘的长度， 确定测量的边缘的长度是否短于预定值，如果确定提取的边缘的长度短于预定值，则提取连接到所提取的边缘的两个顶点，并且重新设计匹配的设计模式 两个提取的顶点的位置彼此相对。

公开(公告)号：US20090077530A1

公开(公告)日：2009-03-19

申请号：US12269705

申请日：2008-11-12

申请人： TOSHIYA KOTANI ,  Shigeki Nojima ,  Shimon Maeda

发明人： TOSHIYA KOTANI ,  Shigeki Nojima ,  Shimon Maeda

IPC分类号： G06F17/50

CPC分类号： G03F1/36

摘要： A design pattern correcting method of correcting a design pattern in relation to a minute step of the design pattern, is disclosed, which comprises extracting at least one of two edges extended from a vertex of the design pattern, measuring a length of the extracted edge, determining whether or not the length of the measured edge is shorter than a predetermined value, extracting two vertexes connected to the extracted edge if it is determined that the length of the extracted edge is shorter than the predetermined value, and reshaping the design pattern to match positions of the two extracted vertexes with each other.

公开(公告)号：US20090077529A1

公开(公告)日：2009-03-19

申请号：US12269687

申请日：2008-11-12

申请人： TOSHIYA KOTANI ,  Shigeki Nojima ,  Shimon Maeda

发明人： TOSHIYA KOTANI ,  Shigeki Nojima ,  Shimon Maeda

IPC分类号： G06F17/50

CPC分类号： G03F1/36

摘要： A design pattern correcting method of correcting a design pattern in relation to a minute step of the design pattern, is disclosed, which comprises extracting at least one of two edges extended from a vertex of the design pattern, measuring a length of the extracted edge, determining whether or not the length of the measured edge is shorter than a predetermined value, extracting two vertexes connected to the extracted edge if it is determined that the length of the extracted edge is shorter than the predetermined value, and reshaping the design pattern to match positions of the two extracted vertexes with each other.

摘要翻译： 公开了一种相对于设计图案的微小步骤校正设计图案的设计图案校正方法，其包括提取从设计图案的顶点延伸的两个边缘中的至少一个，测量提取的边缘的长度， 确定测量的边缘的长度是否短于预定值，如果确定提取的边缘的长度短于预定值，则提取连接到所提取的边缘的两个顶点，并且重新设计匹配的设计模式 两个提取的顶点的位置彼此相对。

公开(公告)号：US20120198396A1

公开(公告)日：2012-08-02

申请号：US13237854

申请日：2011-09-20

申请人： Masanari KAJIWARA ,  Sachiko Kobayashi ,  Satoshi Tanaka ,  Kazuhiro Takahata ,  Shigeki Nojima ,  Toshiya Kotani ,  Shimon Maeda

发明人： Masanari KAJIWARA ,  Sachiko Kobayashi ,  Satoshi Tanaka ,  Kazuhiro Takahata ,  Shigeki Nojima ,  Toshiya Kotani ,  Shimon Maeda

IPC分类号： G06F17/50

CPC分类号： H01L22/20 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of optimizing a semiconductor device manufacturing process according to an embodiment is a method of optimizing a semiconductor device manufacturing process in which a pattern based on circuit design is formed. The method of optimizing a semiconductor device manufacturing process according to the embodiment includes: at the time of calculation of a statistic amount based on a distribution of differences at a plurality of sites between a pattern formed by a first exposing apparatus in a first condition and a pattern formed by a second exposing apparatus in a second condition, calculating the statistic amount after applying weighting to the differences based on information on an electrical characteristic; and repeating the calculating with the second condition being changed, and selecting an condition in which the total sum becomes a minimum or equal to or less than a standard value as an optimized condition of the second exposing apparatus.

摘要翻译： 根据实施例的优化半导体器件制造工艺的方法是优化其中形成基于电路设计的图案的半导体器件制造工艺的方法。 根据实施例的半导体器件制造方法的优化方法包括：在基于在第一状态下由第一曝光装置形成的图案与第一状态之间的多个位置处的差异的分布的统计量的计算时， 在第二状态下由第二曝光装置形成的图案，基于关于电特性的信息对所述差进行加权计算后的统计量; 并重复进行第二条件的计算，并且选择总和变为最小或等于或小于标准值的条件作为第二曝光装置的优化条件。

公开(公告)号：US07949967B2

公开(公告)日：2011-05-24

申请号：US12269705

申请日：2008-11-12

申请人： Toshiya Kotani ,  Shigeki Nojima ,  Shimon Maeda

发明人： Toshiya Kotani ,  Shigeki Nojima ,  Shimon Maeda

IPC分类号： G06F17/50

CPC分类号： G03F1/36

摘要： A design pattern correcting method of correcting a design pattern in relation to a minute step of the design pattern, is disclosed, which comprises extracting at least one of two edges extended from a vertex of the design pattern, measuring a length of the extracted edge, determining whether or not the length of the measured edge is shorter than a predetermined value, extracting two vertexes connected to the extracted edge if it is determined that the length of the extracted edge is shorter than the predetermined value, and reshaping the design pattern to match positions of the two extracted vertexes with each other.

摘要翻译： 公开了一种相对于设计图案的微小步骤校正设计图案的设计图案校正方法，其包括提取从设计图案的顶点延伸的两个边缘中的至少一个，测量提取的边缘的长度， 确定测量的边缘的长度是否短于预定值，如果确定提取的边缘的长度短于预定值，则提取连接到所提取的边缘的两个顶点，并且重新设计匹配的设计模式 两个提取的顶点的位置彼此。

公开(公告)号：US20100191357A1

公开(公告)日：2010-07-29

申请号：US12630048

申请日：2009-12-03

申请人： Shimon Maeda ,  Masahiro Miyairi ,  Soichi Inoue

发明人： Shimon Maeda ,  Masahiro Miyairi ,  Soichi Inoue

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

摘要： A graph in which patterns are each regarded as nodes and nodes of patterns adjacent to each other at a first distance are connected with each other by an edge is produced, each of the patterns is classified into two types so that the two patterns corresponding to the nodes at both ends of the edge are types different to each other, a classification result is corrected by grouping the patterns in each node cluster connected by the edge or each node cluster connected via the node by the edge, and by inverting each of types of a pattern belonging to a same group as that of one pattern, out of a pair of patterns that are classified into a same type and that belong to respectively different groups adjacent to each other at a second distance, and a pattern layout diagram is created based on the corrected classification result.

摘要翻译： 每个图形被认为是在第一距离处彼此相邻的图案的节点和节点之间的图形被生成，每个图案被分成两种类型，使得对应于 边缘两端的节点是彼此不同的类型，分类结果通过将由边缘连接的每个节点簇中的模式或通过该节点连接的每个节点集合的边缘分组，并将每种类型的 在一对图案中属于与一种图案相同的组合的图案，其分为相同类型并且分别属于彼此相邻的第二距离的不同组，并且基于图案布局图 对正确的分类结果。

公开(公告)号：US20090031262A1

公开(公告)日：2009-01-29

申请号：US12179735

申请日：2008-07-25

申请人： Shimon Maeda ,  Suigen Kyoh ,  Soichi Inoue

发明人： Shimon Maeda ,  Suigen Kyoh ,  Soichi Inoue

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A mask pattern formation method and apparatus capable of performing OPC and lithography verification and obtaining OPC result, and a lithography mask are provided. The method of forming a mask pattern from a design layout of a semiconductor integrated circuit comprises inputting a design layout, performing first OPC on the design layout, calculating a first evaluation value for a finished planar shape of a resist pattern corresponding to the design layout based on the first OPC, determining whether the first evaluation value satisfies a predetermined value, if the first evaluation value does not satisfy the predetermined value, locally altering the design layout, performing second OPC on the altered design layout, calculating a second evaluation value for the altered design layout, performing second determination, and if the second evaluation value satisfies the predetermined value, outputting the result of OPC and the first and second evaluation values.

摘要翻译： 提供了能够执行OPC和光刻验证并获得OPC结果的掩模图案形成方法和装置，以及光刻掩模。 从半导体集成电路的设计布局形成掩模图案的方法包括输入设计布局，在设计布局上执行第一OPC，计算与设计布局相对应的抗蚀剂图案的成品平面形状的第一评估值 在第一OPC上，确定第一评估值是否满足预定值，如果第一评估值不满足预定值，则局部改变设计布局，在改变的设计布局上执行第二OPC，计算第二评估值 改变设计布局，执行第二确定，以及如果第二评估值满足预定值，则输出OPC的结果以及第一和第二评估值。

公开(公告)号：US08195697B2

公开(公告)日：2012-06-05

申请号：US12354594

申请日：2009-01-15

申请人： Shimon Maeda ,  Noriyuki Honda

发明人： Shimon Maeda ,  Noriyuki Honda

IPC分类号： G06F7/00

CPC分类号： G06F17/5045

摘要： A database creation method relating to semiconductor ICs, the database registering function block cells constituting a design data of semiconductor IC and evaluation values corresponding to the function block cells such that the function block cells are associated with the evaluation values, for each of the semiconductor ICs, the creation method includes judging whether or not that function block cells constituting a design data of desired semiconductor IC include an unregistered function block cell which is not registered in the database, calculating an unregistered evaluation value corresponding to the unregistered function block cell when the function block cells constituting the design data of the desired semiconductor IC are judged to include the unregistered function block cell, and updating the database by registering the unregistered function block cell and the unregistered evaluation value such that the unregistered function block cell is associated with the unregistered evaluation value.

摘要翻译： 关于半导体IC的数据库创建方法，构成半导体IC的设计数据的数据库登记功能块单元和与功能块单元相对应的评估值，使得功能块单元与评估值相关联，用于每个半导体IC 所述创建方法包括判断构成所需半导体IC的设计数据的功能块单元是否包括未登记在数据库中的未注册功能块单元，计算与未注册功能块单元相对应的未注册评估值， 判断构成期望的半导体IC的设计数据的块单元包括未注册的功能块单元，并且通过注册未注册的功能块单元和未注册的评估值来更新数据库，使得未注册的功能块单元与未注册的评估相关联 价值。

公开(公告)号：US07752595B2

公开(公告)日：2010-07-06

申请号：US11892764

申请日：2007-08-27

申请人： Shimon Maeda ,  Koujirou Ohyoshi

发明人： Shimon Maeda ,  Koujirou Ohyoshi

IPC分类号： G06F17/50

CPC分类号： G03F1/36 ,  G03F1/70

摘要： A pattern producing method includes specifying a first pattern and a second pattern obtained by modifying the first pattern, specifying a correction area based on the second pattern, in a part of an area including the first pattern and the second pattern, producing at least a part of the first pattern, which is included in the correction area, as a correction target pattern, producing a part of the first or second pattern, which is not included in the correction area, as a correction reference pattern, correcting the correction target pattern on the basis of the correction target pattern and the correction reference pattern, and producing a pattern based on the corrected correction target pattern and the second pattern.

摘要翻译： 图案生成方法包括：在包括第一图案和第二图案的区域的一部分中指定通过修改第一图案而获得的第一图案和第二图案，该第一图案和第二图案指定基于第二图案的校正区域， 包括在校正区域中的第一图案作为校正目标图案，产生不包括在校正区域中的第一或第二图案的一部分作为校正参考图案，校正校正目标图案 校正目标图案和校正参考图案的基础，并且基于校正的校正目标图案和第二图案产生图案。

公开(公告)号：US20090037852A1

公开(公告)日：2009-02-05

申请号：US12180244

申请日：2008-07-25

申请人： Sachiko KOBAYASHI ,  Suigen Kyoh ,  Shimon Maeda

发明人： Sachiko KOBAYASHI ,  Suigen Kyoh ,  Shimon Maeda

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： A pattern data generation method of an aspect of the present invention, the method includes creating at least one modification guide to modify a modification target point contained in pattern data, evaluating the modification guides on the basis of an evaluation item, the evaluation item being a change in the shape of the pattern data for the modification target point caused by the modification based on the modification guides or a change in electric characteristics of a pattern formed in accordance with the pattern data, selecting a predetermined modification guide from among the modification guides on the basis of the evaluation result of the modification guides, and modifying the modification target point in accordance with the selected modification guide.

摘要翻译： 本发明的一个方式的图形数据生成方法，该方法包括创建至少一个修改指南，以修改包含在图案数据中的修改目标点，基于评估项目评估修改指南，评估项目是 基于修改引导引起的修改目标点的图案数据的形状的改变或根据图案数据形成的图案的电特性的变化，从修改引导件中选择预定的修改指南 修改指南的评估结果的基础，以及根据所选择的修改指南修改修改目标点。