发明申请
- 专利标题： METHOD AND STRUCTURE FOR IMPROVING DEVICE PERFORMANCE VARIATION IN DUAL STRESS LINER TECHNOLOGY
- 专利标题（中）： 改进双应力衬管技术中设备性能变化的方法与结构
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申请号： US12328358申请日： 2008-12-04
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公开(公告)号： US20090079011A1公开(公告)日： 2009-03-26
- 发明人: Dureseti Chidambarrao , Brian J. Greene
- 申请人： Dureseti Chidambarrao , Brian J. Greene
- 申请人地址： US NY Armonk
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： US NY Armonk
- 主分类号： H01L27/088
- IPC分类号： H01L27/088 ; H01L21/311
摘要：
A method and semiconductor structure that overcome the dual stress liner boundary problem, without significantly increasing the overall size of the integrated circuit, are provided. In accordance with the present invention, the dual stress liner boundary or gap therebetween is forced to land on a neighboring dummy gate region. By forcing the dual stress liner boundary or gap between the liners to land on the dummy gate region, the large stresses associated with the dual stress liner boundary or gap are transferred to the dummy gate region, not the semiconductor substrate. Thus, the impact of the dual stress liner boundary on the nearest neighboring FET is reduced. Additionally, benefits of device variability and packing density are achieved utilizing the present invention.
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