发明申请
- 专利标题: Stacking die package structure for semiconductor devices and method of the same
- 专利标题(中): 堆叠半导体器件的封装结构及其方法
-
申请号: US11984781申请日: 2007-11-21
-
公开(公告)号: US20090127686A1公开(公告)日: 2009-05-21
- 发明人: Wen-Kun Yang , Chi-Yu Wang , Hsien-Wen Hsu
- 申请人: Wen-Kun Yang , Chi-Yu Wang , Hsien-Wen Hsu
- 专利权人: Advanced Chip Engineering Technology Inc.
- 当前专利权人: Advanced Chip Engineering Technology Inc.
- 主分类号: H01L23/488
- IPC分类号: H01L23/488 ; H01L21/58
摘要:
The present invention disclosed a first multi-die package structure for semiconductor devices, the structure comprises a substrate having die receiving window and inter-connecting through holes formed therein; a first level semiconductor die formed under a second level semiconductor die by back-to-back scheme and within the die receiving window, wherein the first multi-die package includes first level contact pads formed under the first level semiconductor die having a first level build up layer formed there-under to couple to a first bonding pads of the first level semiconductor die; a second level contact pads formed on the second level semiconductor die having a second level build up layer formed thereon to couple to second bonding pads of the second level semiconductor die; and conductive bumps formed under the first level build up layer.
信息查询
IPC分类: