发明申请
US20090140762A1 LAYOUT FOR DUT ARRAYS USED IN SEMICONDUCTOR WAFER TESTING
审中-公开
在半导体波形测试中使用的DUT阵列的布局
- 专利标题： LAYOUT FOR DUT ARRAYS USED IN SEMICONDUCTOR WAFER TESTING
- 专利标题（中）： 在半导体波形测试中使用的DUT阵列的布局
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申请号： US12368603申请日： 2009-02-10
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公开(公告)号： US20090140762A1公开(公告)日： 2009-06-04
- 发明人: Christopher Hess , Angelo Rossoni , Stefano Tonello , Michele Squicciarini , Michele Quarantelli
- 申请人： Christopher Hess , Angelo Rossoni , Stefano Tonello , Michele Squicciarini , Michele Quarantelli
- 申请人地址： US CA San Jose
- 专利权人： PDF Solutions, Inc.
- 当前专利权人： PDF Solutions, Inc.
- 当前专利权人地址： US CA San Jose
- 主分类号： G01R31/26
- IPC分类号： G01R31/26
摘要：
A layout for devices under test formed on a semiconductor wafer for use in wafer testing includes a first array of devices under test and a first pad set formed adjacent to the first array. The first pad set includes a gate force pad, a source pad, and a drain pad. Each of the devices under test in the first array is connected to the gate pad of the first pad set. Each of the devices under test in the first array is connected to the source pad of the first pad set. Each of the devices under test in the first array is connected to the drain pad of the first pad set.