公开(公告)号：US20070075718A1

公开(公告)日：2007-04-05

申请号：US11243016

申请日：2005-10-03

申请人： Christopher Hess ,  Angelo Rossoni ,  Stefano Tonello ,  Michele Squicciarini ,  Michele Quarantelli

发明人： Christopher Hess ,  Angelo Rossoni ,  Stefano Tonello ,  Michele Squicciarini ,  Michele Quarantelli

IPC分类号： G01R31/26

CPC分类号： H01L22/34 ,  G01R31/2884 ,  H01L2924/0002 ,  H01L2924/00

摘要： A layout for devices under test formed on a semiconductor wafer for use in wafer testing includes a first array of devices under test and a first pad set formed adjacent to the first array. The first pad set includes a gate force pad, a source pad, and a drain pad. Each of the devices under test in the first array is connected to the gate pad of the first pad set. Each of the devices under test in the first array is connected to the source pad of the first pad set. Each of the devices under test in the first array is connected to the drain pad of the first pad set.

摘要翻译： 在用于晶片测试的半导体晶片上形成的被测器件的布局包括被测试器件的第一阵列和与第一阵列相邻形成的第一焊盘组。 第一焊盘组包括栅极力焊盘，源极焊盘和漏极焊盘。 第一阵列中被测试的每个器件连接到第一焊盘组的栅极焊盘。 第一阵列中被测试的每个设备连接到第一焊盘组的源焊盘。 第一阵列中被测试的每个器件连接到第一焊盘组的漏极焊盘。

公开(公告)号：US20090140762A1

公开(公告)日：2009-06-04

申请号：US12368603

申请日：2009-02-10

申请人： Christopher Hess ,  Angelo Rossoni ,  Stefano Tonello ,  Michele Squicciarini ,  Michele Quarantelli

发明人： Christopher Hess ,  Angelo Rossoni ,  Stefano Tonello ,  Michele Squicciarini ,  Michele Quarantelli

IPC分类号： G01R31/26

CPC分类号： H01L22/34 ,  G01R31/2884 ,  H01L2924/0002 ,  H01L2924/00

摘要： A layout for devices under test formed on a semiconductor wafer for use in wafer testing includes a first array of devices under test and a first pad set formed adjacent to the first array. The first pad set includes a gate force pad, a source pad, and a drain pad. Each of the devices under test in the first array is connected to the gate pad of the first pad set. Each of the devices under test in the first array is connected to the source pad of the first pad set. Each of the devices under test in the first array is connected to the drain pad of the first pad set.

摘要翻译： 在用于晶片测试的半导体晶片上形成的被测器件的布局包括被测试器件的第一阵列和与第一阵列相邻形成的第一焊盘组。 第一焊盘组包括栅极力焊盘，源极焊盘和漏极焊盘。 第一阵列中被测试的每个器件连接到第一焊盘组的栅极焊盘。 第一阵列中被测试的每个设备连接到第一焊盘组的源焊盘。 第一阵列中被测试的每个器件连接到第一焊盘组的漏极焊盘。

公开(公告)号：US07489151B2

公开(公告)日：2009-02-10

申请号：US11243016

申请日：2005-10-03

申请人： Christopher Hess ,  Angelo Rossoni ,  Stefano Tonello ,  Michele Squicciarini ,  Michele Quarantelli

发明人： Christopher Hess ,  Angelo Rossoni ,  Stefano Tonello ,  Michele Squicciarini ,  Michele Quarantelli

IPC分类号： G01R31/02 ,  G01R31/26

CPC分类号： H01L22/34 ,  G01R31/2884 ,  H01L2924/0002 ,  H01L2924/00

摘要： A layout for devices under test formed on a semiconductor wafer for use in wafer testing includes a first array of devices under test and a first pad set formed adjacent to the first array. The first pad set includes a gate force pad, a source pad, and a drain pad. Each of the devices under test in the first array is connected to the gate pad of the first pad set. Each of the devices under test in the first array is connected to the source pad of the first pad set. Each of the devices under test in the first array is connected to the drain pad of the first pad set.

摘要翻译： 在用于晶片测试的半导体晶片上形成的被测器件的布局包括被测试器件的第一阵列和与第一阵列相邻形成的第一焊盘组。 第一焊盘组包括栅极力焊盘，源极焊盘和漏极焊盘。 第一阵列中被测试的每个器件连接到第一焊盘组的栅极焊盘。 第一阵列中被测试的每个设备连接到第一焊盘组的源焊盘。 第一阵列中被测试的每个器件连接到第一焊盘组的漏极焊盘。