中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

67 records (took 0.04 seconds)

    Method and configuration for connecting test structures or line arrays for monitoring integrated circuit manufacturing
    1.
    发明授权
    Method and configuration for connecting test structures or line arrays for monitoring integrated circuit manufacturing 有权
    用于连接用于监控集成电路制造的测试结构或线阵列的方法和配置

    公开(公告)号：US08178876B2

    公开(公告)日：2012-05-15

    申请号：US10595384

    申请日：2004-04-30

    Applicant: Christopher Hess ,  David Goldman

    Inventor： Christopher Hess ,  David Goldman

    IPC: H01L23/58

    CPC classification number: H01L22/34 ,  G01R31/2884 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    Abstract: A test chip comprises at least one level having an array of regions. Each region is capable of including at least one test structure. At least some of the regions include respective test structures. The level has a plurality of driver lines that provide input signals to the test structures. The level has a plurality of receiver lines that receive output signals from the test structures. The level has a plurality of devices for controlling current flow. Each test structure is connected to at least one of the driver lines with a first one of the devices in between. Each test structure is connected to at least one of the receiver lines with a second one of the devices in between, so that each of the test structures can be individually addressed for testing using the driver lines and receiver lines.

    Abstract translation: 测试芯片包括具有区域阵列的至少一个级别。 每个区域能够包括至少一个测试结构。 至少一些区域包括相应的测试结构。 电平具有多个驱动线，其向测试结构提供输入信号。 电平具有接收来自测试结构的输出信号的多个接收线。 该电平具有用于控制电流的多个装置。 每个测试结构都与至少一个驱动器线连接，其中的第一个设备之间。 每个测试结构与至少一个接收器线路连接，其间具有第二个设备，使得每个测试结构可以被单独寻址，以便使用驱动器线路和接收器线路进行测试。

    METHOD AND CONFIGURATION FOR CONNECTING TEST STRUCTURES OR LINE ARRAYS FOR MONITORING INTEGRATED CIRCUIT MANUFACTURING
    2.
    发明申请
    METHOD AND CONFIGURATION FOR CONNECTING TEST STRUCTURES OR LINE ARRAYS FOR MONITORING INTEGRATED CIRCUIT MANUFACTURING 有权
    用于连接测试结构或线阵列用于监控集成电路制造的方法和配置

    公开(公告)号：US20090037131A1

    公开(公告)日：2009-02-05

    申请号：US10595384

    申请日：2004-04-30

    Applicant: Christopher Hess ,  David Goldman

    Inventor： Christopher Hess ,  David Goldman

    IPC: G06F19/00

    CPC classification number: H01L22/34 ,  G01R31/2884 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    Abstract: A test chip comprises at least one level having an array of regions. Each region is capable of including at least one test structure. At least some of the regions include respective test structures. The level has a plurality of driver lines that provide input signals to the test structures. The level has a plurality of receiver lines that receive output signals from the test structures. The level has a plurality of devices for controlling current flow. Each test structure is connected to at least one of the driver lines with a first one of the devices in between. Each test structure is connected to at least one of the receiver lines with a second one of the devices in between, so that each of the test structures can be individually addressed for testing using the driver lines and receiver lines.

    Abstract translation: 测试芯片包括具有区域阵列的至少一个级别。 每个区域能够包括至少一个测试结构。 至少一些区域包括相应的测试结构。 电平具有多个驱动线，其向测试结构提供输入信号。 电平具有接收来自测试结构的输出信号的多个接收线。 该电平具有用于控制电流的多个装置。 每个测试结构都与至少一个驱动器线连接，其中的第一个设备之间。 每个测试结构与至少一个接收器线路连接，其间具有第二个设备，使得每个测试结构可以被单独寻址，以便使用驱动器线路和接收器线路进行测试。

    Methods and apparatus to determine a software application data file and usage
    3.
    发明申请
    Methods and apparatus to determine a software application data file and usage 有权
    确定软件应用程序数据文件和用法的方法和设备

    公开(公告)号：US20070136235A1

    公开(公告)日：2007-06-14

    申请号：US11304527

    申请日：2005-12-14

    Applicant: Christopher Hess

    Inventor： Christopher Hess

    IPC: G06F17/30

    CPC classification number: G06F17/30997 ,  Y10S707/99936 ,  Y10S707/99945 ,  Y10S707/99948

    Abstract: Systems and methods are provided to monitor usage of software applications and services. According to some embodiments, it may be determined that an application event has occurred. At least a portion of a file name may be accessed and compared to one or more actual file identifiers. An actual file identifier may then be selected based on the comparison.

    Abstract translation: 提供系统和方法来监控软件应用程序和服务的使用情况。 根据一些实施例，可以确定已经发生了应用事件。 文件名的至少一部分可以被访问并与一个或多个实际文件标识符进行比较。 然后可以基于比较来选择实际的文件标识符。

    Layout for DUT arrays used in semiconductor wafer testing
    4.
    发明申请
    Layout for DUT arrays used in semiconductor wafer testing 失效
    用于半导体晶圆测试的DUT阵列布局

    公开(公告)号：US20070075718A1

    公开(公告)日：2007-04-05

    申请号：US11243016

    申请日：2005-10-03

    Applicant: Christopher Hess ,  Angelo Rossoni ,  Stefano Tonello ,  Michele Squicciarini ,  Michele Quarantelli

    Inventor： Christopher Hess ,  Angelo Rossoni ,  Stefano Tonello ,  Michele Squicciarini ,  Michele Quarantelli

    IPC: G01R31/26

    CPC classification number: H01L22/34 ,  G01R31/2884 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A layout for devices under test formed on a semiconductor wafer for use in wafer testing includes a first array of devices under test and a first pad set formed adjacent to the first array. The first pad set includes a gate force pad, a source pad, and a drain pad. Each of the devices under test in the first array is connected to the gate pad of the first pad set. Each of the devices under test in the first array is connected to the source pad of the first pad set. Each of the devices under test in the first array is connected to the drain pad of the first pad set.

    Abstract translation: 在用于晶片测试的半导体晶片上形成的被测器件的布局包括被测试器件的第一阵列和与第一阵列相邻形成的第一焊盘组。 第一焊盘组包括栅极力焊盘，源极焊盘和漏极焊盘。 第一阵列中被测试的每个器件连接到第一焊盘组的栅极焊盘。 第一阵列中被测试的每个设备连接到第一焊盘组的源焊盘。 第一阵列中被测试的每个器件连接到第一焊盘组的漏极焊盘。

Patent Agency Ranking