A hardware based wake-up scheme initiates memory power-up upon a normal access to a powered down memory. The access that triggered the power-up is buffered. Further accesses are stalled until the memory is completely powered up. The buffered access then proceeds to the memory and the processor is brought out of stall. In cases where the software does not directly control access to the memory, such as on a cache miss, this scheme avoids undesirable conditions due to access to powered down memories.