发明申请
US20090252269A1 DIGITAL RADIO PROCESSOR ARCHITECTURE WITH REDUCED DCO MODULATION RANGE REQUIREMENT
有权
具有减少DCO调制范围要求的数字无线电处理器架构
- 专利标题: DIGITAL RADIO PROCESSOR ARCHITECTURE WITH REDUCED DCO MODULATION RANGE REQUIREMENT
- 专利标题(中): 具有减少DCO调制范围要求的数字无线电处理器架构
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申请号: US12060886申请日: 2008-04-02
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公开(公告)号: US20090252269A1公开(公告)日: 2009-10-08
- 发明人: Sarma S. Gunturi , Jawaharlal Tangudu , Sthanunathan Ramakrishnan , Jayawardan Janardhanan , Debapriya Sahu , Subhashish Mukherjee
- 申请人: Sarma S. Gunturi , Jawaharlal Tangudu , Sthanunathan Ramakrishnan , Jayawardan Janardhanan , Debapriya Sahu , Subhashish Mukherjee
- 主分类号: H04L7/00
- IPC分类号: H04L7/00
摘要:
A method of achieving reduced modulation range requirement in a Digitally Controlled Oscillator (DCO) which is deployed as part of a DRP (Digital Radio Processor) and tuned to a tuning frequency range having operating-channel center-frequencies, wherein phase difference between consecutive samples is termed as FCW (Frequency Control Word), uses the steps of digitally modifying and limiting the FCW so that the FCW does not exceed known FCW thresholds, e.g., chosen from π/2, π/4, π/8, and redistributing the FCWs while maintaining a cumulative sum of phases and without significant EVM (Error Vector Magnitude) degradation. The FCW threshold can be chosen arbitrarily and need not be in the form of π/2n. The method uses a FCW limiting algorithm which reduces supply voltage sensitivity of the DCO and enables significant reduction in area of capacitor bank which would be otherwise needed.
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