利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

20 条记录 (耗时 0.029 秒)

    DIGITAL RADIO PROCESSOR ARCHITECTURE WITH REDUCED DCO MODULATION RANGE REQUIREMENT
    1.
    发明申请
    DIGITAL RADIO PROCESSOR ARCHITECTURE WITH REDUCED DCO MODULATION RANGE REQUIREMENT 有权
    具有减少DCO调制范围要求的数字无线电处理器架构

    公开(公告)号：US20090252269A1

    公开(公告)日：2009-10-08

    申请号：US12060886

    申请日：2008-04-02

    申请人： Sarma S. Gunturi ,  Jawaharlal Tangudu ,  Sthanunathan Ramakrishnan ,  Jayawardan Janardhanan ,  Debapriya Sahu ,  Subhashish Mukherjee

    发明人： Sarma S. Gunturi ,  Jawaharlal Tangudu ,  Sthanunathan Ramakrishnan ,  Jayawardan Janardhanan ,  Debapriya Sahu ,  Subhashish Mukherjee

    IPC分类号： H04L7/00

    CPC分类号： H04L27/362 ,  H04L7/0331

    摘要： A method of achieving reduced modulation range requirement in a Digitally Controlled Oscillator (DCO) which is deployed as part of a DRP (Digital Radio Processor) and tuned to a tuning frequency range having operating-channel center-frequencies, wherein phase difference between consecutive samples is termed as FCW (Frequency Control Word), uses the steps of digitally modifying and limiting the FCW so that the FCW does not exceed known FCW thresholds, e.g., chosen from π/2, π/4, π/8, and redistributing the FCWs while maintaining a cumulative sum of phases and without significant EVM (Error Vector Magnitude) degradation. The FCW threshold can be chosen arbitrarily and need not be in the form of π/2n. The method uses a FCW limiting algorithm which reduces supply voltage sensitivity of the DCO and enables significant reduction in area of capacitor bank which would be otherwise needed.

    摘要翻译： 一种在数字控制振荡器（DCO）中实现减少的调制范围要求的方法，其被部署为DRP（数字无线电处理器）的一部分并被调谐到具有操作信道中心频率的调谐频率范围，其中连续样本之间的相位差 被称为FCW（频率控制字），使用数字修改和限制FCW的步骤，使得FCW不超过已知的FCW阈值，例如从pi / 2，pi / 4，pi / 8选择并重新分配 FCW同时保持相位的累积和，并且没有显着的EVM（误差矢量幅度）劣化。 FCW阈值可以任​​意选择，不需要以pi / 2n的形式。 该方法使用FCW限制算法，其降低DCO的电源电压灵敏度，并且能够显着减小电容器组的面积，否则将需要它。

    Digital radio processor architecture with reduced DCO modulation range requirement
    2.
    发明授权
    Digital radio processor architecture with reduced DCO modulation range requirement 有权
    数字无线电处理器架构具有降低的DCO调制范围要求

    公开(公告)号：US08345811B2

    公开(公告)日：2013-01-01

    申请号：US12060886

    申请日：2008-04-02

    申请人： Sarma S. Gunturi ,  Jawaharlal Tangudu ,  Sthanunathan Ramakrishnan ,  Jayawardan Janardhanan ,  Debapriya Sahu ,  Subhashish Mukherjee

    发明人： Sarma S. Gunturi ,  Jawaharlal Tangudu ,  Sthanunathan Ramakrishnan ,  Jayawardan Janardhanan ,  Debapriya Sahu ,  Subhashish Mukherjee

    IPC分类号： H04L7/00

    CPC分类号： H04L27/362 ,  H04L7/0331

    摘要： A method of achieving reduced modulation range requirement in a Digitally Controlled Oscillator (DCO) which is deployed as part of a DRP (Digital Radio Processor) and tuned to a tuning frequency range having operating-channel center-frequencies, wherein phase difference between consecutive samples is termed as FCW (Frequency Control Word), uses the steps of digitally modifying and limiting the FCW so that the FCW does not exceed known FCW thresholds, e.g., chosen from π/2, π/4, π/8, and redistributing the FCWs while maintaining a cumulative sum of phases and without significant EVM (Error Vector Magnitude) degradation. The FCW threshold can be chosen arbitrarily and need not be in the form of π/2n. The method uses a FCW limiting algorithm which reduces supply voltage sensitivity of the DCO and enables significant reduction in area of capacitor bank which would be otherwise needed.

    摘要翻译： 一种在数字控制振荡器（DCO）中实现减少的调制范围要求的方法，其被部署为DRP（数字无线电处理器）的一部分并被调谐到具有操作信道中心频率的调谐频率范围，其中连续样本之间的相位差 被称为FCW（频率控制字），使用数字修改和限制FCW的步骤，使得FCW不超过已知的FCW阈值，例如从＆pgr; / 2，＆pgr; / 4，＆pgr / 并重新分配FCW，同时保持相位的累积和，并且没有显着的EVM（误差向量幅度）劣化。 FCW阈值可以任​​意选择，不需要以＆pgr / 2n的形式。 该方法使用FCW限制算法，其降低DCO的电源电压灵敏度，并且能够显着减小电容器组的面积，否则将需要它。

    Attitude estimation for pedestrian navigation using low cost mems accelerometer in mobile applications, and processing methods, apparatus and systems
    5.
    发明授权
    Attitude estimation for pedestrian navigation using low cost mems accelerometer in mobile applications, and processing methods, apparatus and systems 有权
    在移动应用中使用低成本mems加速度计的行人导航姿态估计，以及处理方法，装置和系统

    公开(公告)号：US08694251B2

    公开(公告)日：2014-04-08

    申请号：US13301913

    申请日：2011-11-22

    申请人： Jayawardan Janardhanan ,  Goutam Dutta ,  Varun Tripuraneni

    发明人： Jayawardan Janardhanan ,  Goutam Dutta ,  Varun Tripuraneni

    IPC分类号： G01C21/10

    CPC分类号： G01C21/16 ,  G01C21/165 ,  G01C21/20 ,  G01C22/006

    摘要： A user-heading determining system (10) for pedestrian use includes a multiple-axis accelerometer (110) having acceleration sensors; a device-heading sensor circuit (115) physically situated in a fixed relationship to the accelerometer (110); an electronic circuit (100) operable to generate signals representing components of acceleration sensed by the accelerometer (110) sensors, and to electronically process at least some part of the signals to produce an estimation of attitude of a user motion with respect to the accelerometer, and further to combine the attitude estimation (750, α) with a device heading estimation (770, ψ) responsive to the device-heading sensor circuit, to produce a user heading estimation (780); and an electronic display (190) responsive to the electronic circuit (100) to display information at least in part based on the user heading estimation. Other systems, circuits and processes are also disclosed.

    摘要翻译： 用于行人使用的用户航向确定系统（10）包括具有加速度传感器的多轴加速度计（110） 物理地位于与所述加速度计（110）固定关系的设备航向传感器电路（115）; 电子电路（100），其可操作以产生表示由所述加速度计（110）传感器感测到的加速度的分量的信号，并且电子处理所述信号的至少一部分以产生相对于所述加速度计的用户运动姿态的估计， 并且进一步将所述姿态估计（750，α）与响应于所述设备航向传感器电路的设备航向估计（770，ψ）组​​合以产生用户航向估计（780）; 以及响应于所述电子电路（100）至少部分地基于所述用户标题估计来显示信息的电子显示器（190）。 还公开了其它系统，电路和过程。

    Achieving high dynamic range in a sigma delta analog to digital converter
    6.
    发明授权
    Achieving high dynamic range in a sigma delta analog to digital converter 有权
    在Σ-Δ模数转换器中实现高动态范围

    公开(公告)号：US08400340B2

    公开(公告)日：2013-03-19

    申请号：US13184570

    申请日：2011-07-18

    申请人： Vineet Mishra ,  Jayawardan Janardhanan ,  Samala Sreekiran ,  Meghna Agrawal

    发明人： Vineet Mishra ,  Jayawardan Janardhanan ,  Samala Sreekiran ,  Meghna Agrawal

    IPC分类号： H03M3/00

    CPC分类号： H03M3/496 ,  H03M3/39 ,  H03M3/464

    摘要： A continuous-time sigma-delta analog to digital converter (CTSD ADC) includes a comparator that samples the time integral of an analog signal at each rising edge and falling edge of a sampling clock. A feedback block, operating as a digital to analog converter, receives the outputs of the comparator and generates corresponding analog signals also at each rising and falling edge of the sampling clock. The feedback blocks are implemented as either switched-resistor or switched-current circuits. High signal-to-noise ratio (SNR) is achieved in the CTSD ADC without the need to use very high sampling clock frequencies. Compensation for excess loop delay is provided using a local feedback technique. In an embodiment, the sigma delta modulator in the CTSD ADC is implemented as a second order loop, and the comparator as a two-level comparator.

    摘要翻译： 连续时间Σ-Δ模数转换器（CTSD ADC）包括在采样时钟的每个上升沿和下降沿采样模拟信号的时间积分的比较器。 作为数模转换器工作的反馈块接收比较器的输出，并在采样时钟的每个上升沿和下降沿也产生相应的模拟信号。 反馈块实现为开关电阻或开关电流电路。 在CTSD ADC中实现了高信噪比（SNR），而不需要使用非常高的采样时钟频率。 使用本地反馈技术提供多余回路延迟的补偿。 在一个实施例中，CTSD ADC中的Σ-Δ调制器被实现为二阶环路，比较器被实现为两电平比较器。

    Digital demodulation of pulse-width modulated signals
    9.
    发明授权
    Digital demodulation of pulse-width modulated signals 有权
    脉冲宽度调制信号的数字解调

    公开(公告)号：US08411804B2

    公开(公告)日：2013-04-02

    申请号：US13031257

    申请日：2011-02-21

    申请人： Karthik Subburaj ,  Anant Shankar Kamath ,  Jayawardan Janardhanan

    发明人： Karthik Subburaj ,  Anant Shankar Kamath ,  Jayawardan Janardhanan

    IPC分类号： H04L27/06 ,  H04L25/06 ,  H04L25/10 ,  H04L7/00

    CPC分类号： H04L25/4902

    摘要： A digital PWM demodulator includes a first set of delay cells to receive a PWM signal and to propagate the PWM signal in a forward direction for a first interval. Delayed signals obtained at the end of the first interval are propagated in the reverse direction through the delay cells for a second interval. A logic zero feeds into the last cell at the start of the second interval. The output of a last cell in the delay cells at the end of the second interval is indicative of a data value modulated on the PWM signal. The digital PWM demodulator includes a second set of delay cells designed to operate identical to the first set of delay cells. The first set of delay cells and the second set of delay cells in conjunction with additional digital circuitry demodulate alternate periods of the PWM signal.

    摘要翻译： 数字PWM解调器包括第一组延迟单元，用于接收PWM信号并且沿正向方向传播PWM信号第一间隔。 在第一间隔结束时获得的延迟信号通过延迟单元反向传播第二间隔。 逻辑零在第二个间隔开始时馈送到最后一个单元格。 在第二间隔结束时，延迟单元中的最后一个单元的输出表示在PWM信号上调制的数据值。 数字PWM解调器包括被设计为与第一组延迟单元相同的第二组延迟单元。 第一组延迟单元和第二组延迟单元结合附加数字电路解调PWM信号的交替周期。

    ATTITUDE ESTIMATION FOR PEDESTRIAN NAVIGATION USING LOW COST MEMS ACCELEROMETER IN MOBILE APPLICATIONS, AND PROCESSING METHODS, APPARATUS AND SYSTEMS
    10.
    发明申请
    ATTITUDE ESTIMATION FOR PEDESTRIAN NAVIGATION USING LOW COST MEMS ACCELEROMETER IN MOBILE APPLICATIONS, AND PROCESSING METHODS, APPARATUS AND SYSTEMS 有权
    在移动应用中使用低成本MEMS加速度计的PEDESTRIAN导航的姿态估计和处理方法，装置和系统

    公开(公告)号：US20120136573A1

    公开(公告)日：2012-05-31

    申请号：US13301913

    申请日：2011-11-22

    申请人： Jayawardan Janardhanan ,  Goutam Dutta ,  Varun Tripuraneni

    发明人： Jayawardan Janardhanan ,  Goutam Dutta ,  Varun Tripuraneni

    IPC分类号： G01C21/16

    CPC分类号： G01C21/16 ,  G01C21/165 ,  G01C21/20 ,  G01C22/006

    摘要： A user-heading determining system (10) for pedestrian use includes a multiple-axis accelerometer (110) having acceleration sensors; a device-heading sensor circuit (115) physically situated in a fixed relationship to the accelerometer (110); an electronic circuit (100) operable to generate signals representing components of acceleration sensed by the accelerometer (110) sensors, and to electronically process at least some part of the signals to produce an estimation of attitude of a user motion with respect to the accelerometer, and further to combine the attitude estimation (750, α) with a device heading estimation (770, ψ) responsive to the device-heading sensor circuit, to produce a user heading estimation (780); and an electronic display (190) responsive to the electronic circuit (100) to display information at least in part based on the user heading estimation. Other systems, circuits and processes are also disclosed.

    摘要翻译： 用于行人使用的用户航向确定系统（10）包括具有加速度传感器的多轴加速度计（110） 物理地位于与所述加速度计（110）固定关系的设备航向传感器电路（115）; 电子电路（100），其可操作以产生表示由所述加速度计（110）传感器感测到的加速度的分量的信号，并且电子处理所述信号的至少一部分以产生相对于所述加速度计的用户运动姿态的估计， 并且进一步将所述姿态估计（750，α）与响应于所述设备航向传感器电路的设备航向估计（770，ψ）组​​合以产生用户航向估计（780）; 以及响应于所述电子电路（100）至少部分地基于所述用户标题估计来显示信息的电子显示器（190）。 还公开了其它系统，电路和过程。