Receiver Block Providing Signal Quality Information in a Communication System with Signal Constellation not Having multiple Symbols in Same Angle
    1.
    发明申请
    Receiver Block Providing Signal Quality Information in a Communication System with Signal Constellation not Having multiple Symbols in Same Angle 审中-公开
    接收器块提供具有信号星座的通信系统中没有相同角度的多个符号的信号质量信息

    公开(公告)号:US20070030915A1

    公开(公告)日:2007-02-08

    申请号:US11161460

    申请日:2005-08-04

    IPC分类号: H04L5/12 H04L27/10 H04L27/22

    摘要: An aspect of the present invention provides signal quality information representing the angular deviations (i.e., based on the phase angle difference between the received symbol and the corresponding decoded symbol (i.e., selected symbol point in a signal constellation)). As a result, a relatively more accurate signal quality information is provided to external component at least in systems in which the signal constellation do not have multiple symbols in the same angle. The computational complexity may also be reduced as a result.

    摘要翻译: 本发明的一个方面提供了表示角度偏差的信号质量信息(即,基于接收符号和对应的解码符号之间的相位角差(即,信号星座中的所选符号点))。 结果,至少在信号星座不具有相同角度的多个符号的系统中,向外部组件提供相对更准确的信号质量信息。 结果也可能减少计算复杂度。

    Mitigation circuitry generating cross correlation doppler/code LAG variable comparison value
    2.
    发明授权
    Mitigation circuitry generating cross correlation doppler/code LAG variable comparison value 有权
    产生互相关多普勒/代码LAG变量比较值的缓解电路

    公开(公告)号:US09036683B2

    公开(公告)日:2015-05-19

    申请号:US12719965

    申请日:2010-03-09

    IPC分类号: H04B1/00 H04B1/7075 G01S19/21

    摘要: A receiver (100) is provided for signals of different signal strengths and modulated with respective pseudorandom noise (PN) codes. The receiver (100) includes a correlator circuit (120) operable to correlate the signals with a selectable locally-issued PN code having a Doppler and a code lag to produce a peak, the correlator circuit (120) being subject to cross correlation with a distinct PN code carried by least one of the signals that can produce cross correlation; and a cross correlation circuit (370, 400) operable to generate a variable comparison value related to the cross correlation as a function of values representing a Doppler difference and a code lag difference between the locally-issued PN code and the distinct PN code, and to use the variable comparison value to reject the peak as invalid from cross correlation or to pass the peak as a valid received peak.

    摘要翻译: 为不同信号强度的信号提供接收机(100),并用各自的伪随机噪声(PN)码进行调制。 接收器(100)包括相关器电路(120),其可操作以将信号与具有多普勒和码滞后的可选择本地发出的PN码相关以产生峰值,所述相关器电路(120)与 不同PN码携带的信号中至少有一个会产生互相关; 以及互相关电路(370,400),其可操作以根据表示本地发出的PN码和不同PN码之间的多普勒差和码滞差的值产生与互相关的可变比较值,以及 使用可变比较值将峰值从互相关中排除为无效,或将峰值作为有效接收峰值传递。

    Radio receiver with mitigation modules and mixers with phase compensation
    3.
    发明授权
    Radio receiver with mitigation modules and mixers with phase compensation 有权
    带缓解模块的无线电接收器和具有相位补偿的混频器

    公开(公告)号:US08693598B2

    公开(公告)日:2014-04-08

    申请号:US13204618

    申请日:2011-08-05

    IPC分类号: H03D1/04

    摘要: Example embodiments of the systems and methods of dynamic spur mitigation for wireless receivers disclosed herein comprise one or more of a detection module for detecting the presence of a spur and a determination of its frequency, a complex notch filter chain, and a frequency locked loop which ensures that the input spur is notch filtered even if it drifts after detection. When a spur is detected, the frequency of the tone is determined. The spur is then filtered, for example using a phase rotator and a DC separator. The phase rotation is removed in a subsequent stage. The non-DC component from the DC separator is used to track the spur to compensate for any shifting or drifting in the spur.

    摘要翻译: 本文公开的用于无线接收机的动态杂散减轻的系统和方法的示例性实施例包括用于检测杂散的存在和其频率的确定的检测模块,复杂陷波滤波器链和频率锁定环中的一个或多个 确保即使在检测到漂移后,输入杂散也被陷波滤波。 当检测到杂音时,确定音调的频率。 然后过滤杂质,例如使用相旋转器和DC分离器。 在后续阶段中除去相位旋转。 来自DC分离器的非直流分量用于跟踪支线以补偿支线中的任何变化或漂移。

    CLOCK DRIFT PROFILE DETERMINATION IN NAVIGATION SYSTEM RECEIVERS
    4.
    发明申请
    CLOCK DRIFT PROFILE DETERMINATION IN NAVIGATION SYSTEM RECEIVERS 有权
    导航系统接收器中的时钟变化简档确定

    公开(公告)号:US20130099967A1

    公开(公告)日:2013-04-25

    申请号:US13280524

    申请日:2011-10-25

    IPC分类号: G01S19/23

    CPC分类号: G01S19/23

    摘要: Navigation system receiver, and test circuits and methods for determining drift profile of a receiver clock in the navigation system receiver are disclosed. In an embodiment, the navigation system receiver includes a clock source configured to generate a receiver clock for the navigation system receiver and a test circuit. The test circuit is configured to facilitate determination of a drift profile associated with the receiver clock based on detection and tracking of a test signal received by the test circuit, where the test signal comprises at least one continuous wave (CW) signal.

    摘要翻译: 导航系统接收机,以及用于确定导航系统接收机中的接收机时钟的漂移曲线的测试电路和方法。 在一个实施例中,导航系统接收器包括配置成为导航系统接收器和测试电路产生接收机时钟的时钟源。 测试电路被配置为便于基于由测试电路接收的测试信号的检测和跟踪来确定与接收机时钟相关联的漂移曲线,其中测试信号包括至少一个连续波(CW)信号。

    Circuits, devices, and processes for improved positioning satellite reception and other spread spectrum reception
    5.
    发明授权
    Circuits, devices, and processes for improved positioning satellite reception and other spread spectrum reception 有权
    用于改进定位卫星接收和其他扩频接收的电路,设备和过程

    公开(公告)号:US08934522B2

    公开(公告)日:2015-01-13

    申请号:US13481439

    申请日:2012-05-25

    IPC分类号: H04B1/00

    摘要: An integrated circuit for facilitating spread spectrum reception of data having a data bit period includes an hypothesis search circuit (120, 210, 220) operable to correlate a pseudorandom code with a signal input based on a received signal to produce correlation results, and a processor circuit (320) operable to coherently integrate the correlation results over plural sample windows (PreD1, PreD2) staggered relative to each other in the coherent integration interval and to non-coherently combine the coherently integrated results corresponding to the plural sample windows (PreD1, PreD2) to produce a received signal output, whereby enhancing performance. Other circuits, receivers and processes are also disclosed.

    摘要翻译: 一种用于促进具有数据位周期的数据的扩频接收的集成电路包括可操作以将伪随机码与基于接收信号输入的信号相关联以产生相关结果的假设检索电路(120,210,220),以及处理器 电路(320)可操作以将相关结果相干地整合在相干积分间隔中相对于彼此交错的多个样本窗口(PreD1,PreD2),并且非相干地组合对应于多个样本窗口的相干整合结果(PreD1,PreD2 )以产生接收信号输出,从而提高性能。 还公开了其他电路,接收器和处理。

    Clock drift profile determination in navigation system receivers
    6.
    发明授权
    Clock drift profile determination in navigation system receivers 有权
    导航系统接收机中的时钟漂移曲线确定

    公开(公告)号:US08847819B2

    公开(公告)日:2014-09-30

    申请号:US13280524

    申请日:2011-10-25

    IPC分类号: G01S19/23

    CPC分类号: G01S19/23

    摘要: Navigation system receiver, and test circuits and methods for determining drift profile of a receiver clock in the navigation system receiver are disclosed. In an embodiment, the navigation system receiver includes a clock source configured to generate a receiver clock for the navigation system receiver and a test circuit. The test circuit is configured to facilitate determination of a drift profile associated with the receiver clock based on detection and tracking of a test signal received by the test circuit, where the test signal comprises at least one continuous wave (CW) signal.

    摘要翻译: 导航系统接收机,以及用于确定导航系统接收机中的接收机时钟的漂移曲线的测试电路和方法。 在一个实施例中,导航系统接收器包括配置成为导航系统接收器和测试电路产生接收机时钟的时钟源。 测试电路被配置为便于基于由测试电路接收的测试信号的检测和跟踪来确定与接收机时钟相关联的漂移曲线,其中测试信号包括至少一个连续波(CW)信号。

    Maintaining ADC input magnitude from digital par and peak value
    7.
    发明授权
    Maintaining ADC input magnitude from digital par and peak value 有权
    从数字参考值和峰值维持ADC输入幅度

    公开(公告)号:US08582699B2

    公开(公告)日:2013-11-12

    申请号:US12698173

    申请日:2010-02-02

    IPC分类号: H04L27/08

    摘要: Automatic gain control in a receiver. A method for controlling operating range of an analog-to-digital converter (ADC) by an automatic gain control circuit includes estimating a peak-to-average ratio corresponding to an analog signal from digital samples of the analog signal. The method includes determining a peak value corresponding to the analog signal based on the peak-to-average ratio. Further, the method includes maintaining magnitude of the analog signal at an input of the ADC and gain of the receiver based on the peak value.

    摘要翻译: 接收机自动增益控制。 用于通过自动增益控制电路控制模数转换器(ADC)的操作范围的方法包括从模拟信号的数字样本估计对应于模拟信号的峰均比。 该方法包括基于峰均比来确定与模拟信号相对应的峰值。 此外,该方法包括基于峰值来维持ADC的输入处的模拟信号的幅度和接收机的增益。

    AUTOMATIC GAIN CONTROL IN A RECEIVER
    8.
    发明申请
    AUTOMATIC GAIN CONTROL IN A RECEIVER 有权
    接收机自动增益控制

    公开(公告)号:US20110026651A1

    公开(公告)日:2011-02-03

    申请号:US12698173

    申请日:2010-02-02

    IPC分类号: H04L27/08 H03M1/12

    摘要: Automatic gain control in a receiver. A method for controlling operating range of an analog-to-digital converter (ADC) by an automatic gain control circuit includes estimating a peak-to-average ratio corresponding to an analog signal from digital samples of the analog signal. The method includes determining a peak value corresponding to the analog signal based on the peak-to-average ratio. Further, the method includes maintaining magnitude of the analog signal at an input of the ADC and gain of the receiver based on the peak value.

    摘要翻译: 接收机自动增益控制。 用于通过自动增益控制电路控制模数转换器(ADC)的操作范围的方法包括从模拟信号的数字样本估计对应于模拟信号的峰均比。 该方法包括基于峰均比来确定与模拟信号相对应的峰值。 此外,该方法包括基于峰值来维持ADC的输入处的模拟信号的幅度和接收机的增益。

    PARALLEL SEARCH CIRCUIT FOR A MEDICAL IMPLANT RECEIVER
    9.
    发明申请
    PARALLEL SEARCH CIRCUIT FOR A MEDICAL IMPLANT RECEIVER 审中-公开
    用于医疗植入物接收器的并行搜索电路

    公开(公告)号:US20100036460A1

    公开(公告)日:2010-02-11

    申请号:US12536562

    申请日:2009-08-06

    IPC分类号: A61N1/08 H04B1/16

    CPC分类号: A61N1/3727

    摘要: Parallel search circuit for a medical implant receiver. The circuit includes a radio frequency receiver that receives a first set of contents of a band of channels. The circuit also includes a processing circuit coupled to the radio frequency receiver to process in parallel a second set of contents of a plurality of channels of the band of channels and to detect a signal in the band of channels.

    摘要翻译: 用于医疗植入物接收器的并行搜索电路。 该电路包括接收频道频带的第一组内容的射频接收机。 电路还包括耦合到射频接收机的处理电路并行处理频道频带的多个信道的第二组内容并且检测频道频带中的信号。

    DIGITAL RADIO PROCESSOR ARCHITECTURE WITH REDUCED DCO MODULATION RANGE REQUIREMENT
    10.
    发明申请
    DIGITAL RADIO PROCESSOR ARCHITECTURE WITH REDUCED DCO MODULATION RANGE REQUIREMENT 有权
    具有减少DCO调制范围要求的数字无线电处理器架构

    公开(公告)号:US20090252269A1

    公开(公告)日:2009-10-08

    申请号:US12060886

    申请日:2008-04-02

    IPC分类号: H04L7/00

    CPC分类号: H04L27/362 H04L7/0331

    摘要: A method of achieving reduced modulation range requirement in a Digitally Controlled Oscillator (DCO) which is deployed as part of a DRP (Digital Radio Processor) and tuned to a tuning frequency range having operating-channel center-frequencies, wherein phase difference between consecutive samples is termed as FCW (Frequency Control Word), uses the steps of digitally modifying and limiting the FCW so that the FCW does not exceed known FCW thresholds, e.g., chosen from π/2, π/4, π/8, and redistributing the FCWs while maintaining a cumulative sum of phases and without significant EVM (Error Vector Magnitude) degradation. The FCW threshold can be chosen arbitrarily and need not be in the form of π/2n. The method uses a FCW limiting algorithm which reduces supply voltage sensitivity of the DCO and enables significant reduction in area of capacitor bank which would be otherwise needed.

    摘要翻译: 一种在数字控制振荡器(DCO)中实现减少的调制范围要求的方法,其被部署为DRP(数字无线电处理器)的一部分并被调谐到具有操作信道中心频率的调谐频率范围,其中连续样本之间的相位差 被称为FCW(频率控制字),使用数字修改和限制FCW的步骤,使得FCW不超过已知的FCW阈值,例如从pi / 2,pi / 4,pi / 8选择并重新分配 FCW同时保持相位的累积和,并且没有显着的EVM(误差矢量幅度)劣化。 FCW阈值可以任​​意选择,不需要以pi / 2n的形式。 该方法使用FCW限制算法,其降低DCO的电源电压灵敏度,并且能够显着减小电容器组的面积,否则将需要它。