发明申请
US20090291540A1 CMOS Process with Optimized PMOS and NMOS Transistor Devices
有权
CMOS工艺与优化的PMOS和NMOS晶体管器件
- 专利标题： CMOS Process with Optimized PMOS and NMOS Transistor Devices
- 专利标题（中）： CMOS工艺与优化的PMOS和NMOS晶体管器件
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申请号： US12125855申请日： 2008-05-22
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公开(公告)号： US20090291540A1公开(公告)日： 2009-11-26
- 发明人: Da Zhang , Srikanth B. Samavedam , Voon-Yew Thean , Xiangdong Chen
- 申请人： Da Zhang , Srikanth B. Samavedam , Voon-Yew Thean , Xiangdong Chen
- 主分类号： H01L21/8238
- IPC分类号： H01L21/8238 ; H01L21/336
摘要：
A semiconductor process and apparatus includes forming NMOS and PMOS transistors (24, 34) with enhanced hole mobility in the channel region of a transistor by selectively relaxing part of a biaxial-tensile strained semiconductor layer (90) in a PMOS device area (97) to form a relaxed semiconductor layer (91), and then epitaxially growing a bi-axially stressed silicon germanium channel region layer (22) prior to forming the NMOS and PMOS gate structures (26, 36) overlying the channel regions, and then depositing a contact etch stop layer (53-56) over the NMOS and PMOS gate structures. Embedded silicon germanium source/drain regions (84) may also be formed adjacent to the PMOS gate structure (70) to provide an additional uni-axial stress to the bi-axially stressed channel region.
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