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公开(公告)号：US20090291540A1
公开(公告)日：2009-11-26
申请号：US12125855
申请日：2008-05-22
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/823814 , H01L29/1054 , H01L29/6659 , H01L29/66636 , H01L29/66651 , H01L29/7843 , H01L29/7848
摘要： A semiconductor process and apparatus includes forming NMOS and PMOS transistors (24, 34) with enhanced hole mobility in the channel region of a transistor by selectively relaxing part of a biaxial-tensile strained semiconductor layer (90) in a PMOS device area (97) to form a relaxed semiconductor layer (91), and then epitaxially growing a bi-axially stressed silicon germanium channel region layer (22) prior to forming the NMOS and PMOS gate structures (26, 36) overlying the channel regions, and then depositing a contact etch stop layer (53-56) over the NMOS and PMOS gate structures. Embedded silicon germanium source/drain regions (84) may also be formed adjacent to the PMOS gate structure (70) to provide an additional uni-axial stress to the bi-axially stressed channel region.
摘要翻译： 半导体工艺和装置包括通过选择性地缓解PMOS器件区域（97）中的双轴拉伸应变半导体层（90）的一部分，在晶体管的沟道区域中形成具有增强的空穴迁移率的NMOS和PMOS晶体管（24,34） 以形成松弛半导体层（91），然后在形成覆盖沟道区域的NMOS和PMOS栅极结构（26,36）之前外延生长双轴向应力硅锗沟道区域层（22），然后沉积 接触蚀刻停止层（53-56）在NMOS和PMOS栅极结构之上。 也可以在PMOS栅极结构（70）附近形成嵌入硅锗源极/漏极区（84），以向双轴向应力沟道区提供额外的单轴应力。
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公开(公告)号：US08003454B2
公开(公告)日：2011-08-23
申请号：US12125855
申请日：2008-05-22
IPC分类号： H01L21/336 , H01L21/337
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/823814 , H01L29/1054 , H01L29/6659 , H01L29/66636 , H01L29/66651 , H01L29/7843 , H01L29/7848
摘要： A semiconductor process and apparatus includes forming NMOS and PMOS transistors (24, 34) with enhanced hole mobility in the channel region of a transistor by selectively relaxing part of a biaxial-tensile strained semiconductor layer (90) in a PMOS device area (97) to form a relaxed semiconductor layer (91), and then epitaxially growing a bi-axially stressed silicon germanium channel region layer (22) prior to forming the NMOS and PMOS gate structures (26, 36) overlying the channel regions, and then depositing a contact etch stop layer (53-56) over the NMOS and PMOS gate structures. Embedded silicon germanium source/drain regions (84) may also be formed adjacent to the PMOS gate structure (70) to provide an additional uni-axial stress to the bi-axially stressed channel region.
摘要翻译： 半导体工艺和装置包括通过选择性地缓解PMOS器件区域（97）中的双轴拉伸应变半导体层（90）的一部分，在晶体管的沟道区域中形成具有增强的空穴迁移率的NMOS和PMOS晶体管（24,34） 以形成松弛半导体层（91），然后在形成覆盖沟道区域的NMOS和PMOS栅极结构（26,36）之前外延生长双轴向应力硅锗沟道区域层（22），然后沉积 接触蚀刻停止层（53-56）在NMOS和PMOS栅极结构之上。 也可以在PMOS栅极结构（70）附近形成嵌入硅锗源极/漏极区（84），以向双轴向应力沟道区提供额外的单轴应力。
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公开(公告)号：US20090289280A1
公开(公告)日：2009-11-26
申请号：US12125853
申请日：2008-05-22
IPC分类号： H01L27/092 , H01L21/336 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/1054 , H01L29/165 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： A semiconductor process and apparatus includes forming channel orientation PMOS transistors (34) with enhanced hole mobility in the channel region of a transistor by epitaxially growing a bi-axially stressed silicon germanium channel region layer (22), alone or in combination with an underlying silicon carbide layer (86), prior to forming a PMOS gate structure (36) overlying the channel region layer, and then depositing a neutral (53) or compressive (55) contact etch stop layer over the PMOS gate structure. Embedded silicon germanium source/drain regions (84) may also be formed adjacent to the PMOS gate structure (70) to provide an additional uni-axial stress to the bi-axially stressed channel region.
摘要翻译： 半导体工艺和装置包括通过外延生长双轴向应力的硅锗沟道区域层（22）来形成具有增强的晶体管沟道区中的空穴迁移率的<100>沟道取向PMOS晶体管（34），单独或与 在形成覆盖在沟道区域层上的PMOS栅极结构（36）之前，然后在PMOS栅极结构上沉积中性（53）或压缩（55）接触蚀刻停止层之后的底层碳化硅层（86）。 也可以在PMOS栅极结构（70）附近形成嵌入硅锗源极/漏极区（84），以向双轴向应力沟道区提供额外的单轴应力。
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公开(公告)号：US20090286387A1
公开(公告)日：2009-11-19
申请号：US12122178
申请日：2008-05-16
IPC分类号： H01L21/28 , H01L21/4763 , H01L21/3205
CPC分类号： H01L21/823842 , H01L21/28088 , H01L29/4975
摘要： A semiconductor process and apparatus fabricate a metal gate electrode by forming a first conductive layer (14) over a gate dielectric layer (12) and then selectively introducing nitrogen into the portions of the first conductive layer (14) in the PMOS device region (1), either by annealing (42) a nitrogen-containing diffusion layer (22) formed in the PMOS device region (1) or by performing an ammonia anneal process (82) while the NMOS device region (2) is masked. By introducing nitrogen into the first conductive layer (14), the work function is modulated toward PMOS band edge.
摘要翻译： 一种半导体工艺和装置，通过在栅介质层（12）上形成第一导电层（14）制造金属栅电极，然后选择性地将氮引入PMOS器件区域（1）中的第一导电层（14）的部分 ），通过在形成于PMOS器件区域（1）中的含氮扩散层（22）退火（42），或者在NMOS器件区域（2）被掩蔽的同时执行氨退火工艺（82）。 通过将氮引入到第一导电层（14）中，功函数被调制到PMOS带边缘。
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公开(公告)号：US20090242944A1
公开(公告)日：2009-10-01
申请号：US12059286
申请日：2008-03-31
IPC分类号： H01L29/00 , H01L21/8234
CPC分类号： H01L21/324 , H01L21/823412 , H01L29/045 , H01L29/6659 , H01L29/7833 , H01L29/7847
摘要： A stress memorization technique (SMT) film is deposited over a semiconductor device. The SMT film is annealed with a low thermal budget anneal that is sufficient to create and transfer the stress of the SMT film to the semiconductor device. The SMT film is then removed. After the SMT film is removed, a second anneal is applied to the semiconductor device sufficiently long and at a sufficiently high temperature to activate dopants implanted for forming device source/drains. The result of this approach is that there is minimal gate dielectric growth in the channel along the border of the channel.
摘要翻译： 应力记忆技术（SMT）膜沉积在半导体器件上。 SMT薄膜通过低热预算退火进行退火，该退火足以产生并将SMT薄膜的应力转移到半导体器件。 然后去除SMT膜。 在去除SMT膜之后，对半导体器件施加足够长的时间并在足够高的温度下进行第二次退火以激活植入用于形成器件源极/漏极的掺杂剂。 这种方法的结果是沿通道边界的通道中存在最小的栅介质生长。
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公开(公告)号：US07858482B2
公开(公告)日：2010-12-28
申请号：US12059286
申请日：2008-03-31
IPC分类号： H01L21/336
CPC分类号： H01L21/324 , H01L21/823412 , H01L29/045 , H01L29/6659 , H01L29/7833 , H01L29/7847
摘要： A stress memorization technique (SMT) film is deposited over a semiconductor device. The SMT film is annealed with a low thermal budget anneal that is sufficient to create and transfer the stress of the SMT film to the semiconductor device. The SMT film is then removed. After the SMT film is removed, a second anneal is applied to the semiconductor device sufficiently long and at a sufficiently high temperature to activate dopants implanted for forming device source/drains. The result of this approach is that there is minimal gate dielectric growth in the channel along the border of the channel.
摘要翻译： 应力记忆技术（SMT）膜沉积在半导体器件上。 SMT薄膜通过低热预算退火进行退火，该退火足以产生并将SMT薄膜的应力转移到半导体器件。 然后去除SMT膜。 在去除SMT膜之后，对半导体器件施加足够长的时间并在足够高的温度下进行第二次退火以激活植入用于形成器件源极/漏极的掺杂剂。 这种方法的结果是沿通道边界的通道中存在最小的栅介质生长。
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公开(公告)号：US20130249015A1
公开(公告)日：2013-09-26
申请号：US13893026
申请日：2013-05-13
IPC分类号： H01L27/092
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823857 , H01L29/1054
摘要： An integrated circuit with devices having dielectric layers with different thicknesses. The dielectric layers include a high-k dielectric and some of the dielectric layers include an oxide layer that is formed from an oxidation process. Each device includes a layer including germanium or carbon located underneath the electrode stack of the device. A silicon cap layers is located over the layer including germanium or carbon.
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公开(公告)号：US08178401B2
公开(公告)日：2012-05-15
申请号：US11530058
申请日：2006-09-08
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： A method of fabricating a MOS transistor that comprises a dual-metal gate that is formed from heterotypical metals. A gate dielectric (34), such as HfO2, is deposited on a semiconductor substrate. A sacrificial layer (35), is next deposited over the gate dielectric. The sacrificial layer is patterned so that the gate dielectric over a first (pMOS, for example) area (32) of the substrate is exposed and gate dielectric over a second (nMOS, for example) area (33) of the substrate continues to be protected by the sacrificial layer. A first gate conductor material (51) is deposited over the remaining sacrificial area and over the exposed gate dielectric. The first gate conductor material is patterned so that first gate conductor material over the second area of the substrate is etched away. The sacrificial layer over the second area prevents damage to the underlying dielectric material as the first gate conductor material is removed.
摘要翻译： 一种制造包括由异型金属形成的双金属栅极的MOS晶体管的方法。 诸如HfO 2的栅极电介质（34）沉积在半导体衬底上。 牺牲层（35）接着沉积在栅极电介质上。 牺牲层被图案化，使得衬底的第一（pMOS，例如）区域（32）上的栅极电介质被暴露，并且衬底的第二（nMOS，例如）区域（33）上的栅极电介质继续是 受牺牲层保护。 第一栅极导体材料（51）沉积在剩余的牺牲区域上并暴露在栅极电介质上。 图案化第一栅极导体材料，使得衬底的第二区域上方的第一栅极导体材料被蚀刻掉。 第二区域上的牺牲层防止在去除第一栅极导体材料时损坏下面的介电材料。
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9.发明授权Process for forming an electronic device including a transistor having a metal gate electrode 失效用于形成包括具有金属栅电极的晶体管的电子器件的工艺公开(公告)号：US07750374B2
公开(公告)日：2010-07-06
申请号：US11559633
申请日：2006-11-14
IPC分类号： H01L29/78
CPC分类号： H01L21/823842 , H01L21/823807 , H01L29/1054
摘要： An electronic device includes an n-channel transistor and a p-channel transistor. The p-channel transistor has a first gate electrode with a first work function and a first channel region including a semiconductor layer immediately adjacent to a semiconductor substrate. In one embodiment, the first work function is less than the valence band of the semiconductor layer. In another embodiment, the n-channel transistor has a second gate electrode with a second work function different from the first work function and closer to a conduction band than a valence band of a second channel region. A process of forming the electronic device includes forming first and second gate electrodes having first and second work functions, respectively. First and second channel regions having a same minority carrier type are associated with the first and second gate electrodes, respectively.
摘要翻译： 电子器件包括n沟道晶体管和p沟道晶体管。 p沟道晶体管具有第一功函数的第一栅电极和包括与半导体衬底紧邻的半导体层的第一沟道区。 在一个实施例中，第一功函数小于半导体层的价带。 在另一个实施例中，n沟道晶体管具有第二栅极，其具有与第一功函数不同的第二功函数，并且比第二沟道区的价带更接近导带。 形成电子器件的工艺包括分别形成具有第一和第二功函数的第一和第二栅电极。 具有相同少数载流子类型的第一和第二沟道区分别与第一和第二栅电极相关联。
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公开(公告)号：US20090108296A1
公开(公告)日：2009-04-30
申请号：US11931565
申请日：2007-10-31
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823857 , H01L29/1054
摘要： An integrated circuit with devices having dielectric layers with different thicknesses. The dielectric layers include a high-k dielectric and some of the dielectric layers include an oxide layer that is formed from an oxidation process. Each device includes a layer including germanium or carbon located underneath the electrode stack of the device. A silicon cap layers is located over the layer including germanium or carbon.
摘要翻译： 具有具有不同厚度的电介质层的器件的集成电路。 电介质层包括高k电介质，并且一些电介质层包括由氧化工艺形成的氧化物层。 每个器件包括位于器件的电极堆叠下方的包含锗或碳的层。 硅层位于包含锗或碳的层之上。
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