公开(公告)号：US09362280B2

公开(公告)日：2016-06-07

申请号：US13893026

申请日：2013-05-13

申请人： Gauri V. Karve ,  Mark D. Hall ,  Srikanth B. Samavedam

发明人： Gauri V. Karve ,  Mark D. Hall ,  Srikanth B. Samavedam

IPC分类号： H01L21/70 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/10

CPC分类号： H01L27/092 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/1054

摘要： An integrated circuit with devices having dielectric layers with different thicknesses. The dielectric layers include a high-k dielectric and some of the dielectric layers include an oxide layer that is formed from an oxidation process. Each device includes a layer including germanium or carbon located underneath the electrode stack of the device. A silicon cap layers is located over the layer including germanium or carbon.

公开(公告)号：US08460996B2

公开(公告)日：2013-06-11

申请号：US11931565

申请日：2007-10-31

申请人： Gauri V. Karve ,  Mark D. Hall ,  Srikanth B. Samavedam

发明人： Gauri V. Karve ,  Mark D. Hall ,  Srikanth B. Samavedam

IPC分类号： H01L21/8242

CPC分类号： H01L27/092 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/1054

摘要： An integrated circuit with devices having dielectric layers with different thicknesses. The dielectric layers include a high-k dielectric and some of the dielectric layers include an oxide layer that is formed from an oxidation process. Each device includes a layer including germanium or carbon located underneath the electrode stack of the device. A silicon cap layers is located over the layer including germanium or carbon.

摘要翻译： 具有具有不同厚度的电介质层的器件的集成电路。 电介质层包括高k电介质，并且一些电介质层包括由氧化工艺形成的氧化物层。 每个器件包括位于器件的电极堆叠下方的包含锗或碳的层。 硅层位于包含锗或碳的层之上。

公开(公告)号：US20080001202A1

公开(公告)日：2008-01-03

申请号：US11427980

申请日：2006-06-30

申请人： James K. Schaeffer ,  David C. Gilmer ,  Mark V. Raymond ,  Philip J. Tobin ,  Srikanth B. Samavedam

发明人： James K. Schaeffer ,  David C. Gilmer ,  Mark V. Raymond ,  Philip J. Tobin ,  Srikanth B. Samavedam

IPC分类号： H01L29/94

CPC分类号： H01L27/1203 ,  H01L21/28105 ,  H01L21/823842 ,  H01L21/84 ,  H01L29/4966 ,  H01L29/517

摘要： A semiconductor device has a gate with three conductive layers over a high K gate dielectric. The first layer is substantially oxygen free. The work function is modulated to the desired work function by a second conductive layer in response to subsequent thermal processing. The second layer is a conductive oxygen-bearing metal. With sufficient thickness of the first layer, there is minimal penetration of oxygen from the second layer through the first layer to adversely impact the gate dielectric but sufficient penetration of oxygen to change the work function to a more desirable level. A third layer, which is metallic, is deposited over the second layer. A polysilicon layer is deposited over the third layer. The third layer prevents the polysilicon layer and the oxygen-bearing layer from reacting together.

摘要翻译： 半导体器件具有在高K栅极电介质上的具有三个导电层的栅极。 第一层基本上是无氧的。 响应于随后的热处理，功函数被第二导电层调制到期望的功函数。 第二层是导电含氧金属。 具有足够的第一层的厚度，氧从第二层穿过第一层的最小穿透而不利地影响栅极电介质，但充分渗入氧气以将功函数改变到更理想的水平。 金属的第三层沉积在第二层上。 多晶硅层沉积在第三层上。 第三层防止多晶硅层和含氧层一起反应。

公开(公告)号：US06894353B2

公开(公告)日：2005-05-17

申请号：US10209523

申请日：2002-07-31

申请人： Srikanth B. Samavedam ,  Philip J. Tobin

发明人： Srikanth B. Samavedam ,  Philip J. Tobin

IPC分类号： H01L21/8238 ,  H01L29/76

CPC分类号： H01L21/823835 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823864

摘要： A first gate (120) and a second gate (122) are preferably PMOS and NMOS transistors, respectively, formed in an n-type well (104) and a p-type well (106). In a preferred embodiment first gate (120) includes a first metal layer (110) of titanium nitride on a gate dielectric (108), a second metal layer (114) of tantalum silicon nitride and a silicon containing layer (116) of polysilicon. Second gate (122) includes second metal layer (114) of a tantalum silicon nitride layer on the gate dielectric (108) and a silicon containing layer (116) of polysilicon. First spacers (124) are formed adjacent the sidewalls of the gates to protect the metals from chemistries used to remove photoresist masks during implant steps. Since the chemistries used are selective to polysilicon, the spacers (124) need not protect the polysilicon capping layers, thereby increasing the process margin of the spacer etch process. The polysilicon cap also facilitates silicidation of the gates.

摘要翻译： 第一栅极（120）和第二栅极（122）分别优选分别形成在n型阱（104）和p型阱（106）中的PMOS和NMOS晶体管。 在优选实施例中，第一栅极（120）包括在栅极电介质（108）上的氮化钛的第一金属层（110），氮化硅钽的第二金属层（114）和多晶硅的含硅层（116）。 第二栅极（122）包括栅极电介质（108）上的氮化硅钽层的第二金属层（114）和多晶硅的含硅层（116）。 邻近门的侧壁形成第一间隔物（124），以在植入步骤期间保护用于去除光致抗蚀剂掩模的化学物质的金属。 由于使用的化学物质对多晶硅是选择性的，间隔物（124）不需要保护多晶硅覆盖层，从而增加间隔物蚀刻工艺的工艺边缘。 多晶硅帽也有利于栅极的硅化。

公开(公告)号：US06475841B1

公开(公告)日：2002-11-05

申请号：US09584963

申请日：2000-06-02

申请人： William J. Taylor, Jr. ,  Srikanth B. Samavedam ,  Nigel Cave

发明人： William J. Taylor, Jr. ,  Srikanth B. Samavedam ,  Nigel Cave

IPC分类号： H01L21311

CPC分类号： H01L29/4916 ,  H01L21/26586 ,  H01L21/28114 ,  H01L21/823437 ,  H01L21/823456 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/42376

摘要： A transistor structure includes a retrograde gate structure (112) that is narrower at the end that interfaces with the gate dielectric (120) than it is at the opposite end and method for manufacture of such a structure. The retrograde gate structure (112) is formed by depositing a layer of gate material (104) that has varying composition in the vertical direction. The differentiation in composition causes varying lateral etch rate characteristics along the vertical direction of the gate structure (112) such that increased etching of the gate material (104) occurs near the interface with the gate dielectric layer (102).

摘要翻译： 晶体管结构包括在与栅极电介质（120）接合的端部处比在相反端更窄的逆向栅极结构（112）和用于制造这种结构的方法。 逆行栅极结构（112）通过在垂直方向上沉积具有不同组成的栅极材料层（104）而形成。 组成的区别导致沿着栅极结构（112）的垂直方向的不同的横向蚀刻速率特性，使得栅极材料（104）的增加的蚀刻发生在与栅极介电层（102）的界面附近。

公开(公告)号：US6039803A

公开(公告)日：2000-03-21

申请号：US806741

申请日：1997-02-27

申请人： Eugene A. Fitzgerald ,  Srikanth B. Samavedam

发明人： Eugene A. Fitzgerald ,  Srikanth B. Samavedam

IPC分类号： C30B25/18 ,  H01L21/20

CPC分类号： C30B25/18 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02521 ,  H01L21/02532 ,  Y10S117/902

摘要： A method of processing semiconductor materials, including providing a monocrystalline silicon substrate having a (001) crystallographic surface orientation; off-cutting the substrate to an orientation from about 2.degree. to about 6.degree. offset towards the [110] direction; and epitaxially growing a relaxed graded layer of a crystalline GeSi on the substrate. A semiconductor structure including a monocrystalline silicon substrate having a (001) crystallographic surface orientation, the substrate being off-cut to an orientation from about 2.degree. to about 6.degree. offset towards the [110] direction; and a relaxed graded layer of a crystalline GeSi which is epitaxially grown on the substrate.

摘要翻译： 一种处理半导体材料的方法，包括提供具有（001）晶面取向的单晶硅衬底; 将基板切割成朝向[110]方向偏移约2°至约6°的取向; 并且在衬底上外延生长结晶GeSi的缓和梯度层。 一种半导体结构，其包括具有（001）结晶表面取向的单晶硅衬底，所述衬底偏离朝向[110]方向偏移约2度至约6度的取向; 以及在衬底上外延生长的结晶GeSi的弛豫梯度层。

公开(公告)号：US20130249015A1

公开(公告)日：2013-09-26

申请号：US13893026

申请日：2013-05-13

申请人： Gauri V. Karve ,  Mark D. Hall ,  Srikanth B. Samavedam

发明人： Gauri V. Karve ,  Mark D. Hall ,  Srikanth B. Samavedam

IPC分类号： H01L27/092

CPC分类号： H01L27/092 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/1054

摘要： An integrated circuit with devices having dielectric layers with different thicknesses. The dielectric layers include a high-k dielectric and some of the dielectric layers include an oxide layer that is formed from an oxidation process. Each device includes a layer including germanium or carbon located underneath the electrode stack of the device. A silicon cap layers is located over the layer including germanium or carbon.

公开(公告)号：US08178401B2

公开(公告)日：2012-05-15

申请号：US11530058

申请日：2006-09-08

申请人： David C. Gilmer ,  Srikanth B. Samavedam ,  Philip J. Tobin

发明人： David C. Gilmer ,  Srikanth B. Samavedam ,  Philip J. Tobin

IPC分类号： H01L21/8238

CPC分类号： H01L21/823842

摘要： A method of fabricating a MOS transistor that comprises a dual-metal gate that is formed from heterotypical metals. A gate dielectric (34), such as HfO2, is deposited on a semiconductor substrate. A sacrificial layer (35), is next deposited over the gate dielectric. The sacrificial layer is patterned so that the gate dielectric over a first (pMOS, for example) area (32) of the substrate is exposed and gate dielectric over a second (nMOS, for example) area (33) of the substrate continues to be protected by the sacrificial layer. A first gate conductor material (51) is deposited over the remaining sacrificial area and over the exposed gate dielectric. The first gate conductor material is patterned so that first gate conductor material over the second area of the substrate is etched away. The sacrificial layer over the second area prevents damage to the underlying dielectric material as the first gate conductor material is removed.

摘要翻译： 一种制造包括由异型金属形成的双金属栅极的MOS晶体管的方法。 诸如HfO 2的栅极电介质（34）沉积在半导体衬底上。 牺牲层（35）接着沉积在栅极电介质上。 牺牲层被图案化，使得衬底的第一（pMOS，例如）区域（32）上的栅极电介质被暴露，并且衬底的第二（nMOS，例如）区域（33）上的栅极电介质继续是 受牺牲层保护。 第一栅极导体材料（51）沉积在剩余的牺牲区域上并暴露在栅极电介质上。 图案化第一栅极导体材料，使得衬底的第二区域上方的第一栅极导体材料被蚀刻掉。 第二区域上的牺牲层防止在去除第一栅极导体材料时损坏下面的介电材料。

公开(公告)号：US07750374B2

公开(公告)日：2010-07-06

申请号：US11559633

申请日：2006-11-14

申请人： Cristiano Capasso ,  Srikanth B. Samavedam ,  Eric J. Verret

发明人： Cristiano Capasso ,  Srikanth B. Samavedam ,  Eric J. Verret

IPC分类号： H01L29/78

CPC分类号： H01L21/823842 ,  H01L21/823807 ,  H01L29/1054

摘要： An electronic device includes an n-channel transistor and a p-channel transistor. The p-channel transistor has a first gate electrode with a first work function and a first channel region including a semiconductor layer immediately adjacent to a semiconductor substrate. In one embodiment, the first work function is less than the valence band of the semiconductor layer. In another embodiment, the n-channel transistor has a second gate electrode with a second work function different from the first work function and closer to a conduction band than a valence band of a second channel region. A process of forming the electronic device includes forming first and second gate electrodes having first and second work functions, respectively. First and second channel regions having a same minority carrier type are associated with the first and second gate electrodes, respectively.

摘要翻译： 电子器件包括n沟道晶体管和p沟道晶体管。 p沟道晶体管具有第一功函数的第一栅电极和包括与半导体衬底紧邻的半导体层的第一沟道区。 在一个实施例中，第一功函数小于半导体层的价带。 在另一个实施例中，n沟道晶体管具有第二栅极，其具有与第一功函数不同的第二功函数，并且比第二沟道区的价带更接近导带。 形成电子器件的工艺包括分别形成具有第一和第二功函数的第一和第二栅电极。 具有相同少数载流子类型的第一和第二沟道区分别与第一和第二栅电极相关联。

公开(公告)号：US20090108296A1

公开(公告)日：2009-04-30

申请号：US11931565

申请日：2007-10-31

申请人： Gauri V. Karve ,  Mark D. Hall ,  Srikanth B. Samavedam

发明人： Gauri V. Karve ,  Mark D. Hall ,  Srikanth B. Samavedam

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L27/092 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/1054

摘要： An integrated circuit with devices having dielectric layers with different thicknesses. The dielectric layers include a high-k dielectric and some of the dielectric layers include an oxide layer that is formed from an oxidation process. Each device includes a layer including germanium or carbon located underneath the electrode stack of the device. A silicon cap layers is located over the layer including germanium or carbon.

摘要翻译： 具有具有不同厚度的电介质层的器件的集成电路。 电介质层包括高k电介质，并且一些电介质层包括由氧化工艺形成的氧化物层。 每个器件包括位于器件的电极堆叠下方的包含锗或碳的层。 硅层位于包含锗或碳的层之上。