发明申请
- 专利标题: DYNAMIC REAL-TIME DELAY CHARACTERIZATION AND CONFIGURATION
- 专利标题(中): 动态实时延迟特征和配置
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申请号: US12208967申请日: 2008-09-11
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公开(公告)号: US20100061166A1公开(公告)日: 2010-03-11
- 发明人: Jun Pin Tan , Wei Yee Koay , Boon Jin Ang , Choong Kit Wong , Guang Sheng Soh
- 申请人: Jun Pin Tan , Wei Yee Koay , Boon Jin Ang , Choong Kit Wong , Guang Sheng Soh
- 申请人地址: US CA San Jose
- 专利权人: ALTERA CORPORATION
- 当前专利权人: ALTERA CORPORATION
- 当前专利权人地址: US CA San Jose
- 主分类号: G11C7/00
- IPC分类号: G11C7/00 ; H03K19/173
摘要:
In mask programmable integrated circuit, such as a structured ASIC, a delay chain provides a delay that is set by a mask programmable switch. The delay chain receives an input to allow the delay mask programmed delay to be overridden using a JTAG controller. This allows testing of different delays. The input may also be provided by a fuse block, so that the fuse block can override the mask programmable switch, thus allowing a delay to be changes after mask programming.
公开/授权文献
- US07787314B2 Dynamic real-time delay characterization and configuration 公开/授权日:2010-08-31
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