公开(公告)号：US20100061166A1

公开(公告)日：2010-03-11

申请号：US12208967

申请日：2008-09-11

申请人： Jun Pin Tan ,  Wei Yee Koay ,  Boon Jin Ang ,  Choong Kit Wong ,  Guang Sheng Soh

发明人： Jun Pin Tan ,  Wei Yee Koay ,  Boon Jin Ang ,  Choong Kit Wong ,  Guang Sheng Soh

IPC分类号： G11C7/00 ,  H03K19/173

CPC分类号： H03K19/1735 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  H03K5/133

摘要： In mask programmable integrated circuit, such as a structured ASIC, a delay chain provides a delay that is set by a mask programmable switch. The delay chain receives an input to allow the delay mask programmed delay to be overridden using a JTAG controller. This allows testing of different delays. The input may also be provided by a fuse block, so that the fuse block can override the mask programmable switch, thus allowing a delay to be changes after mask programming.

摘要翻译： 在掩模可编程集成电路（例如结构化ASIC）中，延迟链提供由掩模可编程开关设置的延迟。 延迟链接收输入以允许使用JTAG控制器覆盖延迟掩码编程的延迟。 这允许测试不同的延迟。 输入也可以由熔丝块提供，使得熔丝块可以覆盖掩模可编程开关，从而允许在掩模编程之后改变延迟。

公开(公告)号：US07787314B2

公开(公告)日：2010-08-31

申请号：US12208967

申请日：2008-09-11

申请人： Jun Pin Tan ,  Wei Yee Koay ,  Boon Jin Ang ,  Choong Kit Wong ,  Guang Sheng Soh

发明人： Jun Pin Tan ,  Wei Yee Koay ,  Boon Jin Ang ,  Choong Kit Wong ,  Guang Sheng Soh

IPC分类号： G11C7/10

CPC分类号： H03K19/1735 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  H03K5/133

摘要： In mask programmable integrated circuit, such as a structured ASIC, a delay chain provides a delay that is set by a mask programmable switch. The delay chain receives an input to allow the delay mask programmed delay to be overridden using a JTAG controller. This allows testing of different delays. The input may also be provided by a fuse block, so that the fuse block can override the mask programmable switch, thus allowing a delay to be changes after mask programming.

摘要翻译： 在掩模可编程集成电路（例如结构化ASIC）中，延迟链提供由掩模可编程开关设置的延迟。 延迟链接收输入以允许使用JTAG控制器覆盖延迟掩码编程的延迟。 这允许测试不同的延迟。 输入也可以由熔丝块提供，使得熔丝块可以覆盖掩模可编程开关，从而允许在掩模编程之后改变延迟。

公开(公告)号：US08400863B1

公开(公告)日：2013-03-19

申请号：US12860734

申请日：2010-08-20

申请人： Zun Yang Tan ,  Wei Yee Koay ,  Boon Jin Ang ,  Tat Mun Lui ,  Eu Geen Chew

发明人： Zun Yang Tan ,  Wei Yee Koay ,  Boon Jin Ang ,  Tat Mun Lui ,  Eu Geen Chew

IPC分类号： G11C8/00

CPC分类号： G11C8/12

摘要： Circuits for a memory array and a method of operating a configurable memory block are disclosed. An embodiment of the disclosed memory circuits includes a first memory block coupled to a second memory block to form an array of memory blocks. Each of the memory blocks has multiple bit lines with a dedicated address decoder coupled to the bit lines from each of the memory blocks. Switches are placed in between the first and second memory blocks such that each of the bit lines from the first memory block is connected to a corresponding bitline from the second memory block through one of the switches. The switches may be used to either connect the second memory block to the first memory block or disconnect the second memory block from the first memory block.

摘要翻译： 公开了用于存储器阵列的电路和操作可配置存储器块的方法。 所公开的存储器电路的实施例包括耦合到第二存储器块以形成存储器块阵列的第一存储器块。 每个存储器块具有多个位线，其中专用地址解码器耦合到来自每个存储器块的位线。 开关被放置在第一和第二存储器块之间，使得来自第一存储器块的每个位线通过其中一个开关连接到来自第二存储器块的相应位线。 交换机可以用于将第二存储器块连接到第一存储器块或将第二存储器块与第一存储器块断开。

公开(公告)号：US07305640B1

公开(公告)日：2007-12-04

申请号：US10987986

申请日：2004-11-12

申请人： Hee Kong Phoon ,  Boon Jin Ang ,  Wei Yee Koay ,  Bee Yee Ng

发明人： Hee Kong Phoon ,  Boon Jin Ang ,  Wei Yee Koay ,  Bee Yee Ng

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A system generates memory unit designs tailored to requirements. The system receives a set of specifications for one or more memory units. The set of specifications includes the memory type, the number of memory access ports, and the data width. The system assembles a memory unit schematic from a library of schematic modules defining memory unit components, including memory cells, address decoders, registers, drivers, sense amplifiers, and optionally self-testing components. The system creates a layout for the memory unit from a library of layout modules corresponding to the library of schematic modules. The library of layout modules includes memory unit floorplans specifying the location of layout modules within a memory unit. The system selects from different memory unit floorplans to create an optimized memory unit layout. The memory unit schematic can be validated using functional testing methods. The system processes the memory unit layout to produce a device configuration.

摘要翻译： 系统生成适合要求的内存单元设计。 系统接收一组或多个存储单元的规格。 该组规范包括内存类型，内存访问端口数量和数据宽度。 该系统从定义存储器单元组件的原理图模块库中组装存储器单元原理图，包括存储器单元，地址解码器，寄存器，驱动器，读出放大器以及可选择的自检部件。 系统从与原理图模块库相对应的布局模块库创建存储单元的布局。 布局模块库包括指定布局模块在存储器单元内的位置的存储单元平面图。 系统从不同的存储单元平面图中选择以创建优化的存储器单元布局。 存储单元原理图可以使用功能测试方法进行验证。 系统处理存储器单元布局以产生器件配置。

公开(公告)号：US08699291B1

公开(公告)日：2014-04-15

申请号：US13415052

申请日：2012-03-08

申请人： Chin Ghee Ch'ng ,  Wei Yee Koay ,  Boon Jin Ang

发明人： Chin Ghee Ch'ng ,  Wei Yee Koay ,  Boon Jin Ang

IPC分类号： G11C5/14

CPC分类号： G11C5/147 ,  G11C5/148

摘要： Circuits and techniques for operating a memory circuit are disclosed. A disclosed circuit includes a memory circuit and a sleep circuit with an output terminal coupled to the memory circuit. The sleep circuit is operable to receive a control signal and further operable to place the memory circuit in different modes of operation. The memory circuit may be placed in either a first mode of operation, a second mode of operation or a third mode of operation based at least partly on the control signal. An input terminal of the sleep circuit is coupled to an output terminal of the control circuit. The control circuit is operable to receive an enable signal and is operable to supply the control signal to the sleep circuit at first, second and third voltage levels during the first, second and third modes of operation, respectively, based on the enable signal and a clock signal.

摘要翻译： 公开了用于操作存储器电路的电路和技术。 所公开的电路包括存储器电路和具有耦合到存储器电路的输出端的睡眠电路。 睡眠电路可操作以接收控制信号并进一步可操作以将存储器电路放置在不同的操作模式中。 存储器电路可以至少部分地基于控制信号放置在第一操作模式，第二操作模式或第三操作模式中。 休眠电路的输入端子耦合到控制电路的输出端子。 控制电路可操作以接收使能信号，并且可操作以分别基于使能信号和第一，第二和第三电压电平在第一，第二和第三工作模式下将控制信号提供给第一，第二和第三电压电平， 时钟信号。

公开(公告)号：US06489817B1

公开(公告)日：2002-12-03

申请号：US09965290

申请日：2001-09-26

申请人： Choong Kit Wong ,  Sammy Cheung ,  Boon Jin Ang

发明人： Choong Kit Wong ,  Sammy Cheung ,  Boon Jin Ang

IPC分类号： H03K2100

CPC分类号： H03K23/68

摘要： A clock divider is described. The clock divider includes: a positive edge triggered state machine having a first input for receiving a first input signal and a first output for providing a first output signal; a negative edge triggered state machine having a second input for receiving a second input signal and a second output for providing a second output signal; and a first combination logic coupled to the positive edge triggered state machine and the negative edge triggered state machine, the first combination logic having a third input for receiving third input signals and a third output for providing a third output signal, where (1) at least one of the first input signal and the second input signal includes an input clock signal having an input clock signal period, (2) the third input signals include the first output signal and the second output signal, and (3) the third output includes an output clock signal having an output clock signal period, where the output clock signal period is a multiple of the input clock signal period.

摘要翻译： 描述了时钟分频器。 时钟分频器包括：正沿触发状态机，具有用于接收第一输入信号的第一输入端和用于提供第一输出信号的第一输出端; 负边缘触发状态机，具有用于接收第二输入信号的第二输入和用于提供第二输出信号的第二输出; 以及耦合到所述正沿触发状态机和所述负沿触发状态机的第一组合逻辑，所述第一组合逻辑具有用于接收第三输入信号的第三输入和用于提供第三输出信号的第三输出，其中（1） 第一输入信号和第二输入信号中的至少一个包括具有输入时钟信号周期的输入时钟信号，（2）第三输入信号包括第一输出信号和第二输出信号，以及（3）第三输出包括 具有输出时钟信号周期的输出时钟信号，其中输出时钟信号周期是输入时钟信号周期的倍数。

公开(公告)号：US08686758B1

公开(公告)日：2014-04-01

申请号：US12423777

申请日：2009-04-14

申请人： Ket Chiew Sia ,  Choong Kit Wong ,  Boon Jin Ang

发明人： Ket Chiew Sia ,  Choong Kit Wong ,  Boon Jin Ang

IPC分类号： H03B1/00 ,  H03K3/00 ,  H03K17/56 ,  H03K17/687 ,  H03K19/094

CPC分类号： H03K19/018585 ,  H03K17/102 ,  H03K17/122 ,  H03K19/018521

摘要： I/O circuits and a method for transmitting different types of I/O signals are disclosed. An embodiment of the I/O circuit comprises multiple transistors with multiple switches coupled to the transistors. The switches may be used to selectively couple the transistors to a power source or to another transistor to form different transistor configurations. The transistors may be configured to form a parallel configuration or a stacked configuration. Stacking up transistors may reduce voltage swings in the transistors and subsequently reduce degradation in the transistors.

摘要翻译： 公开了I / O电路和用于发送不同类型的I / O信号的方法。 I / O电路的实施例包括具有耦合到晶体管的多个开关的多个晶体管。 开关可用于选择性地将晶体管耦合到电源或另一晶体管以形成不同的晶体管配置。 晶体管可以被配置为形成并行配置或堆叠配置。 堆叠晶体管可以减小晶体管中的电压摆幅并随后减小晶体管的劣化。

公开(公告)号：US08151224B1

公开(公告)日：2012-04-03

申请号：US12345187

申请日：2008-12-29

申请人： Boon Jin Ang ,  Kar Keng Chua ,  Choong Kit Wong ,  Kok Yoong Foo ,  Thow Pang Chong

发明人： Boon Jin Ang ,  Kar Keng Chua ,  Choong Kit Wong ,  Kok Yoong Foo ,  Thow Pang Chong

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/64

摘要： A method of designing at IC is described. In one embodiment, the method includes providing an option to select a mask layer set from a plurality of mask layer sets, the plurality of mask layer sets including a first mask layer set and a second mask layer set, where the second mask layer set is an alternative mask layer option to the first mask layer set. In one embodiment, the method further includes receiving a selection from a user choosing a mask layer set from the plurality of mask layer sets. In one embodiment, the receiving occurs after design of the IC and prior to fabrication of the IC. Also, in one embodiment, the plurality of mask layer sets are predetermined mask layer sets. In one embodiment, the first mask layer set is a standard threshold voltage (SVT) mask layer set and the second mask layer set is a high threshold voltage (HVT) mask layer set. In one embodiment, core devices of the SVT mask layer set are SVT devices and some periphery devices of the SVT mask layer set are HVT devices. In one embodiment, hybrid cell (H-cell) devices of the HVT mask layer set are HVT devices and some periphery devices of the HVT mask layer set are HVT devices.

摘要翻译： 描述了一种IC设计方法。 在一个实施例中，该方法包括提供从多个掩模层集合中选择掩模层集合的选项，所述多个掩模层集合包括第一掩模层集合和第二掩模层集合，其中第二掩模层集合是 第一掩模层集合的替代掩模层选项。 在一个实施例中，该方法还包括从用户接收从多个掩模层集合中选择掩模层集合的选择。 在一个实施例中，接收发生在IC的设计之后并且在IC的制造之前。 而且，在一个实施例中，多个掩模层组是预定的掩模层集合。 在一个实施例中，第一掩模层集合是标准阈值电压（SVT）掩模层集合，第二掩模层集合是高阈值电压（HVT）掩模层集合。 在一个实施例中，SVT掩模层集合的核心设备是SVT设备，SVT掩模层集合的一些外围设备是HVT设备。 在一个实施例中，HVT掩模层集合的混合小区（H cell）设备是HVT设备，并且HVT掩模层集合的一些外围设备是HVT设备。

公开(公告)号：US07265587B1

公开(公告)日：2007-09-04

申请号：US11189348

申请日：2005-07-26

申请人： Bee Yee Ng ,  Choong Kit Wong ,  Boon Jin Ang

发明人： Bee Yee Ng ,  Choong Kit Wong ,  Boon Jin Ang

IPC分类号： H03K19/0175

CPC分类号： H03K19/018585 ,  H03K19/01721 ,  H04L25/0264 ,  H04L25/0286

摘要： Methods and apparatus are provided for performing pre-emphasis of signals using buffer circuitry that is not dedicated to LVDS transmission. In an embodiment of the invention, pre-emphasis circuitry is provided to enable unused transistors of the buffer circuitry to increase the current that can be driven onto output signal lines, resulting in sharper signal transitions and improved signal integrity. In addition, circuitry can be provided that limits the duration of the pre-emphasis to a selected period of time, thereby conserving power and limiting the differential voltage between a given pair of transmitted signals.

摘要翻译： 提供的方法和装置用于使用不专用于LVDS传输的缓冲电路来执行信号的预加重。 在本发明的一个实施例中，提供预加重电路以使得缓冲电路的未使用的晶体管能够增加可驱动到输出信号线上的电流，从而产生更清晰的信号转换和改进的信号完整性。 此外，可以提供将预加重的持续时间限制到所选择的时间段的电路，从而节省功率并限制给定的一对发送信号之间的差分电压。

公开(公告)号：US08612814B1

公开(公告)日：2013-12-17

申请号：US12814713

申请日：2010-06-14

申请人： Jun Pin Tan ,  Kiun Kiet Jong ,  Boon Jin Ang

发明人： Jun Pin Tan ,  Kiun Kiet Jong ,  Boon Jin Ang

IPC分类号： G01R31/28

CPC分类号： G11C29/44 ,  G11C11/41 ,  G11C29/40 ,  G11C29/52 ,  G11C2029/0409

摘要： Integrated circuits with error detection circuitry are provided. Integrated circuits may include memory cells organized into frames. The error detection circuitry may compress each frame to scan for soft errors. The error detection circuitry may include multiple input shift registers (MISRs), a data register, and a signature comparator. The data frames may be read, compressed, and shifted into the MISRs in parallel. After all the data frames have been read, the MISRs may provide a scanned MISR signature at their outputs. Computer-aided design (CAD) tools may be used to calculate a precomputed MISR signature. The precomputed MISR signature may be loaded into the data register. The signature comparator compares the scanned MISR signature with the precomputed MISR signature. If the signatures match, then the device is free of soft errors. If the signatures do not match, then at least one soft error exists.

摘要翻译： 提供了具有错误检测电路的集成电路。 集成电路可以包括被组织成帧的存储器单元。 错误检测电路可以压缩每个帧以扫描软错误。 错误检测电路可以包括多个输入移位寄存器（MISR），数据寄存器和签名比较器。 数据帧可以被并行读取，压缩和移入MISR中。 在读取所有数据帧之后，MISR可以在其输出端提供扫描的MISR签名。 计算机辅助设计（CAD）工具可用于计算预计算的MISR签名。 预计算的MISR签名可以加载到数据寄存器中。 签名比较器将扫描的MISR签名与预先计算的MISR签名进行比较。 如果签名匹配，则设备没有软错误。 如果签名不匹配，则至少存在一个软错误。