发明申请
US20100064111A1 INFORMATION PROCESSING DEVICE INCLUDING MEMORY MANAGEMENT DEVICE MANAGING ACCESS FROM PROCESSOR TO MEMORY AND MEMORY MANAGEMENT METHOD
有权
信息处理设备，包括存储器管理设备管理从处理器访问存储器和存储器管理方法
- 专利标题： INFORMATION PROCESSING DEVICE INCLUDING MEMORY MANAGEMENT DEVICE MANAGING ACCESS FROM PROCESSOR TO MEMORY AND MEMORY MANAGEMENT METHOD
- 专利标题（中）： 信息处理设备，包括存储器管理设备管理从处理器访问存储器和存储器管理方法
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申请号： US12555952申请日： 2009-09-09
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公开(公告)号： US20100064111A1公开(公告)日： 2010-03-11
- 发明人: Atsushi Kunimatsu , Hiroto Nakai , Hiroyuki Sakamoto , Kenichi Maeda , Masaki Miyagawa , Hiroshi Nozue , Kazuhiro Kawagome
- 申请人： Atsushi Kunimatsu , Hiroto Nakai , Hiroyuki Sakamoto , Kenichi Maeda , Masaki Miyagawa , Hiroshi Nozue , Kazuhiro Kawagome
- 申请人地址： JP Tokyo
- 专利权人： KABUSHIKI KAISHA TOSHIBA
- 当前专利权人： KABUSHIKI KAISHA TOSHIBA
- 当前专利权人地址： JP Tokyo
- 优先权： JP2008-231363 20080909; JP2009-169371 20090717
- 主分类号： G06F12/00
- IPC分类号： G06F12/00 ; G06F12/16 ; G06F12/02
摘要：
A device according to an example of the invention comprises a section which accepts a write destination logical address and write target data from a processor, the write destination logical address indicating a write position to write the write target data into a composite memory which includes a first memory and a nonvolatile second memory, a section which determines a write destination physical address corresponding to the write destination logical address so that the number of times of access to the second memory is smaller than the number of times of access to the first memory, a section which stores, in a storage section, address conversion data associating the write destination logical address with the write destination physical address, and a section which writes the write target data into a position in the composite memory indicated by the write destination physical address.
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