发明申请
- 专利标题： NON-VOLATILE SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING EMBEDDED NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE WITH SIDEWALL GATE
- 专利标题（中）： 非挥发性半导体器件及其制造嵌入式非易失性半导体存储器件的方法
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申请号： US12652517申请日： 2010-01-05
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公开(公告)号： US20100105199A1公开(公告)日： 2010-04-29
- 发明人: Kan Yasui , Digh Hisamoto , Tetsuya Ishimaru , Shin-Ichiro Kimura
- 申请人： Kan Yasui , Digh Hisamoto , Tetsuya Ishimaru , Shin-Ichiro Kimura
- 专利权人： RENESAS TECHNOLOGY CORP.
- 当前专利权人： RENESAS TECHNOLOGY CORP.
- 优先权： JP2005-178871 20050620
- 主分类号： H01L21/28
- IPC分类号： H01L21/28
摘要：
A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. A select gate electrode to form a side wall in a memory area is formed to be higher than that of the gate electrode in a logic area so that the height of the side wall gate electrode of the self-align split gate memory cell is greater than that of the gate electrode in the logic area. Height reduction for the gate electrode is performed in the logic area before gate electrode formation.
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