公开(公告)号：US08537505B2

公开(公告)日：2013-09-17

申请号：US12784405

申请日：2010-05-20

Applicant: Masato Shiimoto ,  Kan Yasui ,  Nobuo Yoshida ,  Hiroyuki Takazawa

Inventor： Masato Shiimoto ,  Kan Yasui ,  Nobuo Yoshida ,  Hiroyuki Takazawa

IPC: G11B5/39 ,  G11B5/11

CPC classification number: G11B5/3932 ,  B82Y25/00 ,  G01R33/093 ,  G01R33/098 ,  H01L43/08 ,  H01L43/10

Abstract: According to one embodiment, a magnetoresistive effect head includes a lower magnetic shield provided on a substrate, a magnetoresistive effect film laminated from a pinned layer with a pinned direction of magnetization, an intermediate layer, a free layer having a varying direction of magnetization controlled by an applied external magnetic field, a magnetic domain control layer formed with an intervening insulation layer on both sides in a track width direction of the magnetoresistive effect film, an upper magnetic shield, and electrodes for directing sense current flow in a direction perpendicular to a film surface of the magnetoresistive effect film, wherein a magnetic field applied by the magnetic domain control layer to a region away from an ABS of the free layer is at least 1.4 times larger than a magnetic field applied by the magnetic domain control layer to a region near the ABS of the free layer.

Abstract translation: 根据一个实施例，磁阻效应头包括设置在基板上的下磁屏蔽，从具有钉扎方向的钉扎层层压的磁阻效应膜，中间层，具有变化的磁化方向的自由层， 施加的外部磁场，在磁阻效应膜的磁道宽度方向上在两侧形成有中间绝缘层的磁畴控制层，上磁屏蔽和用于引导垂直于膜的方向的感测电流的电极 磁阻效应膜的表面，其中由磁畴控制层施加到远离自由层的ABS的区域的磁场比由磁畴控制层施加到接近的区域的磁场的至少大1.4倍 ABS的自由层。

公开(公告)号：US20130028058A1

公开(公告)日：2013-01-31

申请号：US13641239

申请日：2011-03-28

Applicant: Kan Yasui ,  Harukazu Miyamoto ,  Masukazu Igarashi

Inventor： Kan Yasui ,  Harukazu Miyamoto ,  Masukazu Igarashi

IPC: G11B13/00

CPC classification number: G11B5/3146 ,  G11B5/1278 ,  G11B5/3116 ,  G11B5/314 ,  G11B5/315 ,  G11B2005/0024

Abstract: In a case in which a microwave-assisted magnetic recording system is applied to a shingled write system for recording with high density, the width of a high-frequency generation element is narrower than a track width of main pole, and both steep parts of magnetic field gradients 24 and 25 are overlap each other by performing offset of a high-frequency magnetic field generating unit 17 of the magnetic head for shingled write from the central line of the main pole 8 in the both areas having high magnetic field gradient. At that time, a magnetic field vector 11 from the main pole 8 is perpendicular incident on a film surface of the high-frequency magnetic field generating unit by using means such as a method for arranging a shield material having high magnetic permeability so that main pole magnetic field is corrected and induced, a method for arranging a hard bias layer to which a desired static magnetic field is added, and a method for obliquely forming a high-frequency magnetic field generating unit, thereby performing stable oscillation to realize magnetic recording with high density.

Abstract translation: 在将微波辅助磁记录系统应用于用于高密度记录的带状写入系统的情况下，高频发生元件的宽度窄于主极的轨道宽度，并且两个陡峭部分的磁 通过在具有高磁场梯度的两个区域中从主极8的中心线执行用于带状写入的磁头的高频磁场产生单元17的偏移，场梯度24和25彼此重叠。 此时，来自主极8的磁场矢量11通过使用诸如用于布置具有高磁导率的屏蔽材料的方法的装置而垂直入射在高频磁场产生单元的膜表面上，使得主极 磁场被校正和感应，用于布置添加有期望的静磁场的硬偏置层的方法和用于倾斜地形成高频磁场产生单元的方法，从而执行稳定的振荡以实现高的磁记录 密度。

公开(公告)号：US08063433B2

公开(公告)日：2011-11-22

申请号：US12109340

申请日：2008-04-24

Applicant: Tetsuya Ishimaru ,  Yasuhiro Shimamoto ,  Toshiyuki Mine ,  Yasunobu Aoki ,  Koichi Toba ,  Kan Yasui

Inventor： Tetsuya Ishimaru ,  Yasuhiro Shimamoto ,  Toshiyuki Mine ,  Yasunobu Aoki ,  Koichi Toba ,  Kan Yasui

IPC: H01L29/792

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L29/42344 ,  H01L29/513 ,  H01L29/66833

Abstract: A memory cell includes an ONO film composed of a stacked film of a silicon nitride film SIN which is a charge trapping portion and oxide films BOTOX and TOPOX positioned under and over the silicon nitride film, a memory gate electrode MG over the ONO film, a source region MS, and a drain region MD, and program or erase is performed by hot carrier injection in the memory cell. In the memory cell, a total concentration of N—H bonds and Si—H bonds contained in the silicon nitride film SIN is made to be 5×1020 cm−3 or less.

Abstract translation: 存储单元包括由作为电荷捕获部分的氮化硅膜SIN和位于氮化硅膜下面的氧化物膜BOTOX和TOPOX的叠层膜，ONO膜上的存储栅电极MG， 源区MS和漏区MD，并且通过在存储单元中的热载流子注入来执行编程或擦除。 在存储单元中，氮化硅膜SIN中包含的N-H键和Si-H键的总浓度为5×10 20 cm -3以下。

公开(公告)号：US20110181987A1

公开(公告)日：2011-07-28

申请号：US12997518

申请日：2009-05-19

Applicant: Masato Shiimoto ,  Hiroyuki Katada ,  Takeshi Nakagawa ,  Kan Yasui ,  Yo Sato

Inventor： Masato Shiimoto ,  Hiroyuki Katada ,  Takeshi Nakagawa ,  Kan Yasui ,  Yo Sato

IPC: G11B5/39

CPC classification number: G11B5/3909 ,  B82Y10/00 ,  B82Y25/00 ,  G11B5/3954 ,  G11B2005/3996

Abstract: Provided is a differential type reproduction head which can obtain a preferable bit error rate without causing a baseline shift even when two magnetoresistive elements have different maximum resistance change amounts. The differential type reproduction head has a layered structure formed by a first magnetoresistive element having a first free layer, a differential gap layer, and a second magnetoresistive element having a second free layer. When DR1 and DR2 are the maximum resistance change amounts of the first magnetoresistive element and the second magnetoresistive element, respectively, HB1 is a magnetic domain control field applied to the first free layer, and HB2 is a magnetic domain control field applied to the second free layer, the following relationships are satisfied: HB1>HB2 when DR1>DR2; HB2>HB1 when DR2>DR1.

Abstract translation: 提供了一种差分型再现头，即使当两个磁阻元件具有不同的最大电阻变化量时，也可以获得优选的误码率，而不引起基线偏移。 差分型再现头具有由具有第一自由层，差分间隙层和具有第二自由层的第二磁阻元件的第一磁阻元件形成的分层结构。 当DR1和DR2分别是第一磁阻元件和第二磁阻元件的最大电阻变化量时，HB1分别是施加到第一自由层的磁畴控制场，HB2是施加到第二自由电阻的磁畴控制场 层，满足以下关系：当DR1> DR2时，HB1> HB2; HB2> DR1> DR1时HB1。

公开(公告)号：US20100322013A1

公开(公告)日：2010-12-23

申请号：US12873679

申请日：2010-09-01

Applicant: Tetsuya Ishimaru ,  Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura

Inventor： Tetsuya Ishimaru ,  Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura

IPC: G11C16/04 ,  H01L29/792

CPC classification number: G11C16/0466 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/792

Abstract: In a situation where a memory cell includes an ONO film, which comprises a silicon nitride film for charge storage and oxide films positioned above and below the silicon nitride film; a memory gate above the ONO film; a select gate, which is adjacent to a lateral surface of the memory gate via the ONO film; a gate insulator positioned below the select gate; a source region; and a drain region, an erase operation is performed by injecting holes generated by BTBT into the silicon nitride film while applying a positive potential to the source region, applying a negative potential to the memory gate, applying a positive potential to the select gate, and flowing a current from the drain region to the source region, thus improving the characteristics of a nonvolatile semiconductor memory device.

Abstract translation: 在存储单元包括ONO膜的情况下，其包括用于电荷存储的氮化硅膜和位于氮化硅膜上方和下方的氧化膜; 在ONO电影上方的记忆门; 选择栅极，其经由ONO膜与存储栅的侧表面相邻; 位于选择门下方的栅极绝缘体; 源区; 和漏极区域，通过将BTBT产生的空穴注入氮化硅膜，同时向源极区域施加正电位，向存储栅极施加负电位，向选择栅极施加正电位，进行擦除操作，以及 使电流从漏极区域流向源极区域，从而改善非易失性半导体存储器件的特性。

公开(公告)号：US07847343B2

公开(公告)日：2010-12-07

申请号：US12368538

申请日：2009-02-10

Applicant: Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura ,  Tetsuya Ishimaru

Inventor： Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura ,  Tetsuya Ishimaru

IPC: H01L29/792

CPC classification number: H01L27/11568 ,  G11C16/0433 ,  H01L21/2815 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/1203 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

Abstract: Provided is a nonvolatile semiconductor memory device having a split gate structure, wherein a memory gate is formed over a convex shaped substrate and side surfaces of it is used as a channel. The nonvolatile semiconductor memory device according to the present invention is excellent in read current driving power even if a memory cell is scaled down.

Abstract translation: 提供了一种具有分割栅极结构的非易失性半导体存储器件，其中存储栅极形成在凸形基板上，并且其侧表面用作沟道。 根据本发明的非易失性半导体存储器件即使存储单元按比例缩小也具有优异的读取电流驱动功率。

公开(公告)号：US07751255B2

公开(公告)日：2010-07-06

申请号：US12233670

申请日：2008-09-19

Applicant: Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

Inventor： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC classification number: G11C16/0425 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459

Abstract: An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.

Abstract translation: 提供一种稳定运行半导体非易失性存储器件的操作方案。 当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。 因此，可以验证擦除状态，而不知道任何时变变化。 此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。

公开(公告)号：US07504689B2

公开(公告)日：2009-03-17

申请号：US11182013

申请日：2005-07-15

Applicant: Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura ,  Tetsuya Ishimaru

Inventor： Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura ,  Tetsuya Ishimaru

IPC: H01L29/792

CPC classification number: H01L27/11568 ,  G11C16/0433 ,  H01L21/2815 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/1203 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

Abstract: Provided is a nonvolatile semiconductor memory device having a split gate structure, wherein a memory gate is formed over a convex shaped substrate and side surfaces of it is used as a channel. The nonvolatile semiconductor memory device according to the present invention is excellent in read current driving power even if a memory cell is scaled down.

Abstract translation: 提供了一种具有分割栅极结构的非易失性半导体存储器件，其中存储栅极形成在凸形基板上，并且其侧表面用作沟道。 根据本发明的非易失性半导体存储器件即使存储单元按比例缩小，读取电流驱动功率也优异。

公开(公告)号：US07268042B2

公开(公告)日：2007-09-11

申请号：US11005015

申请日：2004-12-07

Applicant: Digh Hisamoto ,  Kan Yasui

Inventor： Digh Hisamoto ,  Kan Yasui

IPC: H01L21/8247

CPC classification number: H01L27/11526 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11531 ,  H01L29/66825

Abstract: A nonvolatile semiconductor memory device of a split gate structure having a gate of low resistance suitable to the arrangement of a memory cell array is provided. When being formed of a side wall spacer, a memory gate is formed of polycrystal silicon and then replaced with nickel silicide. Thus, its resistance can be lowered with no effect on the silicidation to the selection gate or the diffusion layer.

Abstract translation: 提供了具有适合于存储单元阵列的布置的具有低电阻的栅极的分离栅极结构的非易失性半导体存储器件。 当由侧壁间隔物形成时，存储栅由多晶硅形成，然后被硅化镍替代。 因此，其电阻可以降低，而对选择栅极或扩散层的硅化物没有影响。

公开(公告)号：US20070207581A1

公开(公告)日：2007-09-06

申请号：US11797839

申请日：2007-05-08

Applicant: Kan Yasui ,  Digh Hisamoto ,  Shinichiro Kimura

Inventor： Kan Yasui ,  Digh Hisamoto ,  Shinichiro Kimura

IPC: H01L21/336

CPC classification number: H01L27/11568 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/4232 ,  H01L29/792

Abstract: In a split gate type nonvolatile memory cell in which a MOS transistor for a nonvolatile memory using a charge storing film and a MOS transistor for selecting it are adjacently formed, the charge storing characteristic is improved and the resistance of the gate electrode is reduced. In order to prevent the thickness reduction at the corner portion of the charge storing film and improve the charge storing characteristic, a taper is formed on the sidewall of the select gate electrode. Also, in order to stably perform a silicide process for reducing the resistance of the self-aligned gate electrode, the sidewall of the select gate electrode is recessed. Alternatively, a discontinuity is formed between the upper portion of the self-aligned gate electrode and the upper portion of the select gate electrode.