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    Nonvolatile Semiconductor Memory Device
    2.
    发明申请
    Nonvolatile Semiconductor Memory Device 有权
    非易失性半导体存储器件

    公开(公告)号：US20100322013A1

    公开(公告)日：2010-12-23

    申请号：US12873679

    申请日：2010-09-01

    申请人： Tetsuya Ishimaru ,  Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura

    发明人： Tetsuya Ishimaru ,  Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura

    IPC分类号： G11C16/04 ,  H01L29/792

    CPC分类号： G11C16/0466 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/792

    摘要： In a situation where a memory cell includes an ONO film, which comprises a silicon nitride film for charge storage and oxide films positioned above and below the silicon nitride film; a memory gate above the ONO film; a select gate, which is adjacent to a lateral surface of the memory gate via the ONO film; a gate insulator positioned below the select gate; a source region; and a drain region, an erase operation is performed by injecting holes generated by BTBT into the silicon nitride film while applying a positive potential to the source region, applying a negative potential to the memory gate, applying a positive potential to the select gate, and flowing a current from the drain region to the source region, thus improving the characteristics of a nonvolatile semiconductor memory device.

    摘要翻译： 在存储单元包括ONO膜的情况下，其包括用于电荷存储的氮化硅膜和位于氮化硅膜上方和下方的氧化膜; 在ONO电影上方的记忆门; 选择栅极，其经由ONO膜与存储栅的侧表面相邻; 位于选择门下方的栅极绝缘体; 源区; 和漏极区域，通过将BTBT产生的空穴注入氮化硅膜，同时向源极区域施加正电位，向存储栅极施加负电位，向选择栅极施加正电位，进行擦除操作，以及 使电流从漏极区域流向源极区域，从而改善非易失性半导体存储器件的特性。

    Semiconductor nonvolatile memory device
    4.
    发明授权
    Semiconductor nonvolatile memory device 有权
    半导体非易失性存储器件

    公开(公告)号：US07751255B2

    公开(公告)日：2010-07-06

    申请号：US12233670

    申请日：2008-09-19

    申请人： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

    发明人： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

    IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

    CPC分类号： G11C16/0425 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459

    摘要： An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.

    摘要翻译： 提供一种稳定运行半导体非易失性存储器件的操作方案。 当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。 因此，可以验证擦除状态，而不知道任何时变变化。 此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。

    Non-volatile semiconductor device and method of fabricating embedded non-volatile semiconductor memory device with sidewall gate
    6.
    发明申请
    Non-volatile semiconductor device and method of fabricating embedded non-volatile semiconductor memory device with sidewall gate 有权
    非易失性半导体器件和制造具有侧壁栅极的嵌入式非易失性半导体存储器件的方法

    公开(公告)号：US20070145455A1

    公开(公告)日：2007-06-28

    申请号：US11452256

    申请日：2006-06-14

    申请人： Kan Yasui ,  Digh Hisamoto ,  Tetsuya Ishimaru ,  Shin-ichiro Kimura

    发明人： Kan Yasui ,  Digh Hisamoto ,  Tetsuya Ishimaru ,  Shin-ichiro Kimura

    IPC分类号： H01L29/76

    CPC分类号： H01L27/115 ,  G11C16/0425 ,  H01L27/11568 ,  H01L29/42344

    摘要： A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of an optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. A select gate electrode to form a side wall in a memory area is formed to be higher than that of the gate electrode in a logic area so that the height of the side wall gate electrode of the self-align split gate memory cell is greater than that of the gate electrode in the logic area. Height reduction for the gate electrode is performed in the logic area before gate electrode formation.

    摘要翻译： 提供了一种制造非易失性半导体存储器件的方法，其克服了由于利用侧壁结构同时形成自对准分裂栅型存储单元而导致的最佳栅极高度的差异而引入的注入离子的问题，以及 一个缩放的MOS晶体管。 形成在存储区域中形成侧壁的选择栅电极比逻辑区域中的栅电极高，使得自对准分离栅极存储单元的侧壁栅电极的高度大于 在逻辑区域的栅电极。 栅极电极的高度降低在栅电极形成之前的逻辑区域中进行。

    Nonvolatile semiconductor memory device
    7.
    发明授权
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US07130223B2

    公开(公告)日：2006-10-31

    申请号：US11251963

    申请日：2005-10-18

    申请人： Tetsuya Ishimaru ,  Nozomu Matsuzaki ,  Hitoshi Kume

    发明人： Tetsuya Ishimaru ,  Nozomu Matsuzaki ,  Hitoshi Kume

    IPC分类号： G11C11/34

    CPC分类号： G11C16/0433 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11568 ,  H01L29/513 ,  H01L29/518 ,  H01L29/792

    摘要： Characteristics of a nonvolatile semiconductor memory device are improved. The memory cell comprises: an ONO film constituted by a silicon nitride film SIN for accumulating charge and by oxide films BOTOX and TOPOX disposed thereon and thereunder; a memory gate electrode MG disposed at an upper portion thereof; a select gate electrode SG disposed at a side portion thereof through the ONO film; a gate oxide film SGOX disposed thereunder. By applying a potential to a select gate electrode SG of a memory cell having a source region MS and a drain region MD and to the source region MS and by accelerating electrons flowing in a channel through a high electric field produced between a channel end of the select transistor and an end of an n-type doped region ME disposed under the memory gate electrode MG, hot holes are generated by impact ionization, and the hot holes are injected into a silicon nitride film SIN by a negative potential applied to the memory gate electrode MG, and thereby an erase operation is performed.

    摘要翻译： 提高了非易失性半导体存储器件的特性。 存储单元包括：由用于累积电荷的氮化硅膜SIN和其上设置的氧化膜BOTOX和TOPOX构成的ONO膜; 设置在其上部的存储栅极电极MG; 通过ONO膜设置在其侧部的选择栅电极SG; 设置在其下方的栅氧化膜SGOX。 通过向具有源极区域MS和漏极区域MD的存储单元的选择栅极SG施加电位，并且通过在通道的沟道端之间产生的高电场加速在沟道中流动的电子， 选择晶体管和设置在存储栅电极MG下方的n型掺杂区ME的端部，通过冲击电离产生热孔，并且通过施加到存储栅的负电位将热孔注入氮化硅膜SIN 电极MG，从而进行擦除操作。

    Nonvolatile memory device and semiconductor device
    8.
    发明申请
    Nonvolatile memory device and semiconductor device 有权
    非易失性存储器件和半导体器件

    公开(公告)号：US20060239072A1

    公开(公告)日：2006-10-26

    申请号：US11472993

    申请日：2006-06-23

    申请人： Toshihiro Tanaka ,  Takashi Yamaki ,  Yutaka Shinagawa ,  Daisuke Okada ,  Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru

    发明人： Toshihiro Tanaka ,  Takashi Yamaki ,  Yutaka Shinagawa ,  Daisuke Okada ,  Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru

    IPC分类号： G11C16/04 ,  G11C11/34

    CPC分类号： G11C16/10 ,  G11C16/0433

    摘要： Disclosed here is a method for speeding up data writing and reducing power consumption by reducing the variation of the threshold voltage of each of non-volatile memory cells at data writing. When writing data in a memory cell, a voltage of about 8V is applied to the memory gate line, a voltage of about 5V is applied to the source line, a voltage of about 1.5V is applied to the selected gate line respectively. At that time, in the writing circuit, the writing pulse is 0, the writing latch output a High signal, and a NAND-circuit outputs a Low signal. And, a constant current of about 1 iA flows in a constant current source transistor and the bit line is discharged by a constant current of about 1 iA to flow a current in the memory cell.

    摘要翻译： 这里公开了一种通过在数据写入时减小每个非易失性存储单元的阈值电压的变化来加速数据写入并降低功耗的方法。 当在存储单元中写入数据时，约8V的电压被施加到存储器栅极线，大约5V的电压被施加到源极线，大约1.5V的电压分别施加到所选择的栅极线。 此时，在写入电路中，写入脉冲为0，写入锁存器输出高电平信号，NAND电路输出低电平信号。 并且，在恒定电流源晶体管中流动约1IA的恒定电流，并且通过约1iA的恒定电流放电位线以使存储单元中的电流流动。

    Semiconductor device and manufacturing method for semiconductor device to reduce the lithography masks
    9.
    发明申请
    Semiconductor device and manufacturing method for semiconductor device to reduce the lithography masks 有权
    用于半导体器件的半导体器件和制造方法来减少光刻掩模

    公开(公告)号：US20060035435A1

    公开(公告)日：2006-02-16

    申请号：US11189078

    申请日：2005-07-26

    申请人： Kan Yasui ,  Digh Hisamoto ,  Tetsuya Ishimaru

    发明人： Kan Yasui ,  Digh Hisamoto ,  Tetsuya Ishimaru

    IPC分类号： H01L21/336

    CPC分类号： H01L29/792 ,  G11C16/0466 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11568 ,  H01L29/42344

    摘要： Semiconductor device and manufacturing method for reducing the number of required lithography masks added to the nonvolatile memory in the standard CMOS process to shorten the production period and reduce costs. In a split-gate memory cell with silicided gate electrodes utilizing a sidewall structure, a separate auxiliary pattern is formed adjoining the selected gate electrodes. A contact is set on a wiring layer self-aligned by filling side-wall gates of polysilicon in the gap between the electrodes and auxiliary pattern. The contact may overlap onto the auxiliary pattern and device isolation region, in an optimal design considering the size of the occupied surface area. If the distance to the selected gate electrode is x, the ONO film deposit thickness is t, and the polysilicon film deposit thickness is d, then the auxiliary pattern may be separated just by a distance x such that x

    摘要翻译： 用于减少在标准CMOS工艺中添加到非易失性存储器中的所需光刻掩模的数量的半导体器件和制造方法，以缩短生产周期并降低成本。 在具有利用侧壁结构的硅化栅电极的分裂栅极存储单元中，形成邻接所选择的栅电极的单独的辅助图案。 通过填充电极和辅助图案之间的间隙中的多晶硅的侧壁栅极，将接触设置在自对准的布线层上。 考虑到占用的表面积的大小，接触可以以最佳设计重叠在辅助图案和设备隔离区域上。 如果到选定的栅电极的距离为x，则ONO膜沉积厚度为t，多晶硅膜沉积厚度为d，则辅助图案可以仅分开距离x，使得x <2x（t + d） 。