发明申请
US20100221851A1 TEST STRUCTURE AND METHOD FOR DETECTING CHARGE EFFECTS DURING SEMICONDUCTOR PROCESSING
有权
用于检测半导体加工过程中充电效应的测试结构和方法
- 专利标题： TEST STRUCTURE AND METHOD FOR DETECTING CHARGE EFFECTS DURING SEMICONDUCTOR PROCESSING
- 专利标题（中）： 用于检测半导体加工过程中充电效应的测试结构和方法
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申请号： US12777858申请日： 2010-05-11
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公开(公告)号： US20100221851A1公开(公告)日： 2010-09-02
- 发明人: Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
- 申请人： Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
- 申请人地址： TW Hsinchu
- 专利权人： MACRONIX INTERNATIONAL CO., LTD.
- 当前专利权人： MACRONIX INTERNATIONAL CO., LTD.
- 当前专利权人地址： TW Hsinchu
- 主分类号： H01L21/66
- IPC分类号： H01L21/66
摘要：
A semiconductor process test structure comprises an electrode, a charge-trapping layer, and a diffusion region. The test structure is a capacitor-like structure in which the charge-trapping layer will trap charges during various processing steps. Gate-induced drain leakage (GIDL) measurement techniques can then be used to characterize the charging status of the test structure.