发明申请
US20110012239A1 Barrier Layer On Polymer Passivation For Integrated Circuit Packaging
审中-公开
聚合物钝化阻挡层用于集成电路封装
- 专利标题: Barrier Layer On Polymer Passivation For Integrated Circuit Packaging
- 专利标题(中): 聚合物钝化阻挡层用于集成电路封装
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申请号: US12758311申请日: 2010-04-12
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公开(公告)号: US20110012239A1公开(公告)日: 2011-01-20
- 发明人: Shiqun Gu , Urmi Ray , Yiming Li , Arvind Chandrasekaran
- 申请人: Shiqun Gu , Urmi Ray , Yiming Li , Arvind Chandrasekaran
- 申请人地址: US CA San Diego
- 专利权人: QUALCOMM Incorporated
- 当前专利权人: QUALCOMM Incorporated
- 当前专利权人地址: US CA San Diego
- 主分类号: H01L29/06
- IPC分类号: H01L29/06 ; H01L21/768 ; H01L21/311
摘要:
A barrier layer deposited on the passivation layer of a semiconductor die decreases adhesion of glue used during stacking of semiconductor dies by altering chemical or structural properties of the passivation layer. During detachment of a carrier wafer from a wafer, the barrier layer reduces glue residue on the wafer by modifying the surface of the passivation layer. The barrier layer may be insulating films such as silicon dioxide, silicon nitride, silicon carbide, polytetrafluoroethylene, organic layers, or epoxy and may be less than two micrometers in thickness. Additionally, the barrier layer may be used to reduce topography of the semiconductor die to decrease adhesion of glues.