发明申请
- 专利标题: OFF-CHIP VIAS IN STACKED CHIPS
- 专利标题(中): 堆叠式切片中的切割六边形
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申请号: US12941392申请日: 2010-11-08
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公开(公告)号: US20110049696A1公开(公告)日: 2011-03-03
- 发明人: Belgacem Haba , Ilyas Mohammed , Vage Oganesian , David Ovrutsky , Laura Wills Mirkarimi
- 申请人: Belgacem Haba , Ilyas Mohammed , Vage Oganesian , David Ovrutsky , Laura Wills Mirkarimi
- 申请人地址: US CA San Jose
- 专利权人: TESSERA, INC.
- 当前专利权人: TESSERA, INC.
- 当前专利权人地址: US CA San Jose
- 主分类号: H01L25/11
- IPC分类号: H01L25/11
摘要:
A microelectronic assembly includes first and second stacked microelectronic elements, each having spaced apart traces extending along a front face and beyond at least a first edge thereof. An insulating region can contact the edges of each microelectronic element and at least portions of the traces of each microelectronic element extending beyond the respective first edges. The insulating region can define first and second side surfaces adjacent the first and second edges of the microelectronic elements. A plurality of spaced apart openings can extend along a side surface of the microelectronic assembly. Electrical conductors connected with respective traces can have portions disposed in respective openings and extending along the respective openings. The electrical conductors may extend to pads or solder balls overlying a face of one of the microelectronic elements.
公开/授权文献
- US08076788B2 Off-chip vias in stacked chips 公开/授权日:2011-12-13
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