公开(公告)号：US11430879B2

公开(公告)日：2022-08-30

申请号：US17102098

申请日：2020-11-23

申请人： Tessera, Inc.

发明人： Kangguo Cheng ,  Juntao Li

IPC分类号： H01L29/66 ,  H01L27/12 ,  H01L21/84 ,  H01L21/762 ,  H01L29/417 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/02 ,  H01L21/30 ,  H01L29/08 ,  H01L21/3065 ,  H01L29/04 ,  H01L29/06 ,  H01L29/49

摘要： Described herein is a FinFET device in which epitaxial layers of semiconductor material are formed in source/drain regions on fin portions. The fin portions can be located within a dielectric layer that is deposited on a semiconductor substrate. Surfaces of the fin portions can be oriented in the {100} lattice plane of the crystalline material of the fin portions, providing for good epitaxial growth. Further described are methods for forming the FinFET device.

公开(公告)号：US20220181205A1

公开(公告)日：2022-06-09

申请号：US17571814

申请日：2022-01-10

申请人： Tessera, Inc.

发明人： Benjamin D. Briggs ,  Jessica Dechene ,  Elbert Huang ,  Joe Lee ,  Theodorus E. Standaert

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

摘要： A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.

公开(公告)号：US11342446B2

公开(公告)日：2022-05-24

申请号：US16684115

申请日：2019-11-14

申请人： TESSERA, INC.

发明人： Michael A. Guillorn ,  Terence B. Hook ,  Robert R. Robison ,  Reinaldo A. Vega ,  Rajasekhar Venigalla

IPC分类号： H01L29/66 ,  H01L21/28 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  B82Y10/00 ,  H01L29/775 ,  H01L29/10

摘要： A method of forming a nanosheet device, including forming a channel stack on a substrate, where the channel stack includes at least one nanosheet channel layer and at least one sacrificial release layer, forming a stack cover layer on at least a portion of the channel stack, forming a dummy gate on at least a portion of the stack cover layer, wherein at least a portion of the at least one nanosheet channel layer and at least one sacrificial release layer is exposed on opposite sides of the dummy gate, removing at least a portion of the at least one sacrificial release layer on each side of the dummy gate to form a sacrificial supporting rib, and forming an inner spacer layer on exposed portions of the at least one nanosheet channel layer and at least one sacrificial supporting rib.

公开(公告)号：US11232983B2

公开(公告)日：2022-01-25

申请号：US17011823

申请日：2020-09-03

申请人： Tessera, Inc.

发明人： Daniel C. Edelstein ,  Son V. Nguyen ,  Takeshi Nogami ,  Deepika Priyadarshini ,  Hosadurga K. Shobha

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

摘要： Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.

公开(公告)号：US11222815B2

公开(公告)日：2022-01-11

申请号：US16689223

申请日：2019-11-20

申请人： TESSERA, INC.

发明人： Conal E. Murray ,  Chih-Chao Yang

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  C23F4/00 ,  C23F1/44

摘要： A semiconductor interconnect structure having a first electrically conductive structure having a plurality of bottom portions; a dielectric capping layer, at least a portion of the dielectric capping layer being in contact with a first bottom portion of the plurality of bottom portions; and a second electrically conductive structure in electrical contact with a second bottom portion of the plurality of bottom portions. A method of forming the interconnect structure is also provided.

公开(公告)号：US11101357B2

公开(公告)日：2021-08-24

申请号：US16983764

申请日：2020-08-03

申请人： Tessera, Inc.

发明人： Anthony I. Chou ,  Arvind Kumar ,  Chung-Hsun Lin ,  Shreesh Narasimha ,  Claude Ortolland ,  Jonathan T. Shaw

IPC分类号： H01L29/423 ,  H01L29/51 ,  H01L21/265 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02 ,  H01L21/426 ,  H01L21/8234 ,  H01L21/3115 ,  H01L21/324 ,  H01L21/84 ,  H01L29/40 ,  H01L29/78 ,  H01L21/283 ,  H01L21/308 ,  H01L29/417

摘要： An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

公开(公告)号：US11094824B2

公开(公告)日：2021-08-17

申请号：US16685329

申请日：2019-11-15

申请人： TESSERA, INC.

发明人： Huiming Bu ,  Kangguo Cheng ,  Dechao Guo ,  Sivananda K Kanakasabapathy ,  Peng Xu

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/3065 ,  H01L21/324

摘要： A semiconductor device includes one or more fins. Each fin includes a top channel portion formed from a channel material, and a bottom substrate portion formed from a same material as an underlying substrate. An isolation dielectric layer is formed between and around the bottom substrate portion of the one or more fins. A single oxide layer is formed in direct contact with the bottom substrate portion of each fin, between the bottom substrate portion of each fin and the isolation dielectric layer. A gate dielectric is formed over the one or more fins and between a straight sidewall of at least a top portion of the single oxide layer and an adjacent sidewall of the one or more fins, in contact with both the straight sidewall and the bottom substrate portion.

公开(公告)号：US20210202313A1

公开(公告)日：2021-07-01

申请号：US17181399

申请日：2021-02-22

申请人： Tessera, Inc.

发明人： Lawrence A. Clevenger ,  Carl J. Radens ,  John H. Zhang

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/311

摘要： A semiconductor device includes a first trench on a mandrel line through a top mask layer and stopping at a middle mask layer; and a second trench on a non-mandrel line through the top mask layer and stopping at the middle mask layer. A spacer material is removed from a structure resulting from etching the first trench and the second trench. The device includes a first via structure, formed using a removable material, in the first trench; a second via structure, formed using a removable material, in the second trench; an air-gap formed in a third trench created at a location of the spacer; a fourth trench formed by etching, to remove the first via structure and a first portion of a bottom mask layer under the first via structure; and a self-aligned line-end via on the mandrel line formed by filling the fourth trench with a conductive metal.

公开(公告)号：US11004933B2

公开(公告)日：2021-05-11

申请号：US16042498

申请日：2018-07-23

申请人： TESSERA, INC.

发明人： Josephine B. Chang ,  Bruce B. Doris ,  Michael A. Guillorn ,  Isaac Lauer ,  Xin Miao

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/775 ,  H01L29/786

摘要： Field effect transistors include a stack of nanowires of vertically arranged channel layers. A source and drain region is disposed at respective ends of the vertically arranged channel layers. A gate stack is formed over, around, and between the vertically arranged channel layers. Internal spacers are each formed between the gate stack and a respective source or drain region, with at least one pair of spacers being positioned above an uppermost channel layer.

公开(公告)号：US10964588B2

公开(公告)日：2021-03-30

申请号：US16868475

申请日：2020-05-06

申请人： Tessera, Inc.

发明人： Christopher J. Penny ,  Benjamin David Briggs ,  Huai Huang ,  Lawrence A. Clevenger ,  Michael Rizzolo ,  Hosadurga Shobha

IPC分类号： H01L21/768 ,  H01L23/528

摘要： A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.