Invention Application
- Patent Title: Methods of Forming Integrated Circuit Chips Having Vertically Extended Through-Substrate Vias Therein
- Patent Title (中): 形成具有垂直扩展的基板通孔的集成电路芯片的方法
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Application No.: US12969977Application Date: 2010-12-16
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Publication No.: US20110086486A1Publication Date: 2011-04-14
- Inventor: Ho-Jin Lee , Kang-Wook Lee , Myeong-Soon Park , Ju-il Choi , Son-Kwan Hwang
- Applicant: Ho-Jin Lee , Kang-Wook Lee , Myeong-Soon Park , Ju-il Choi , Son-Kwan Hwang
- Priority: KR2008-54124 20080610
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/02 ; H01L21/28

Abstract:
Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode.
Public/Granted literature
- US08629059B2 Methods of forming integrated circuit chips having vertically extended through-substrate vias therein Public/Granted day:2014-01-14
Information query
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