A memory cell with surrounding word line structures includes an active area; a plurality of first trenches formed on the active area in a first direction, each first trench has a bit line on a sidewall therein; a plurality of second trenches formed on the active area in a second direction, each second trench has two word lines formed correspondingly on the sidewalls in the second trench; and a plurality of transistors formed on the active area. The word line pairs are arranged into a surrounding word line structure. The transistor is controlled by the bit line and the two word lines, thus improving the speed of the transistor.