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    Motor With Rotor Positioning Component
    2.
    发明申请
    Motor With Rotor Positioning Component 有权
    带转子定位元件的电机

    公开(公告)号：US20140210319A1

    公开(公告)日：2014-07-31

    申请号：US13750269

    申请日：2013-01-25

    申请人： Chien-Jung Chen ,  Hsien-Wen Liu ,  Chih-Tsung HSU ,  Tzu-Wen Tsai

    发明人： Chien-Jung Chen ,  Hsien-Wen Liu ,  Chih-Tsung HSU ,  Tzu-Wen Tsai

    IPC分类号： H02K11/00

    CPC分类号： H02K11/0068 ,  H02K11/215

    摘要： A motor includes a base, a rotor unit and a driving unit. The base has opposite first and second surfaces. The rotor unit includes a magnet unit disposed on a rotatable magnet carrier to face the first surface of the base. The driving unit includes induction coils disposed on a circuit board, a sensor unit that is disposed on the circuit board and spaced apart from the induction coils and that defines a first reference line with the rotation axis, and a rotor positioning component disposed on the second surface of the base, extending along a second reference line, and capable of magnet attraction with the magnet unit for positioning the rotor unit relative to the sensor unit when the rotor unit stops rotating.

    摘要翻译： 电动机包括基座，转子单元和驱动单元。 底座具有相对的第一和第二表面。 转子单元包括设置在可旋转的磁体载体上以面向基座的第一表面的磁体单元。 驱动单元包括设置在电路板上的感应线圈，设置在电路板上并与感应线圈隔开并且限定具有旋转轴的第一参考线的传感器单元，以及设置在第二 所述基座的表面沿着第二参考线延伸，并且当所述转子单元停止旋转时，能够与所述磁体单元磁吸引，用于相对于所述传感器单元相对于所述传感器单元定位所述转子单元。

    Memory device having buried bit line and vertical transistor and fabrication method thereof
    3.
    发明授权
    Memory device having buried bit line and vertical transistor and fabrication method thereof 有权
    具有掩埋位线和垂直晶体管的存储器件及其制造方法

    公开(公告)号：US08759907B2

    公开(公告)日：2014-06-24

    申请号：US13094796

    申请日：2011-04-26

    申请人： Tieh-Chiang Wu ,  Yi-Nan Chen ,  Hsien-Wen Liu

    发明人： Tieh-Chiang Wu ,  Yi-Nan Chen ,  Hsien-Wen Liu

    IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L27/108 ,  H01L29/66

    CPC分类号： H01L29/66666 ,  H01L21/2257 ,  H01L27/10876 ,  H01L27/10885 ,  H01L29/7827

    摘要： A method of forming a buried bit line is provided. A substrate is provided and a line-shaped trench region is defined in the substrate. A line-shaped trench is formed in the line-shaped trench region of the substrate. The line-shaped trench includes a sidewall surface and a bottom surface. Then, the bottom surface of the line-shaped trench is widened to form a curved bottom surface. Next, a doping area is formed in the substrate adjacent to the curved bottom surface. Lastly, a buried conductive layer is formed on the doping area such that the doping area and the buried conductive layer together constitute the buried bit line.

    摘要翻译： 提供一种形成掩埋位线的方法。 提供衬底并且在衬底中限定线状沟槽区域。 在基板的线状沟槽区域中形成线状沟槽。 线状沟槽包括侧壁表面和底部表面。 然后，将线状沟槽的底面加宽，形成弯曲的底面。 接下来，在与该弯曲底面相邻的基板上形成掺杂区域。 最后，在掺杂区域上形成掩埋导电层，使得掺杂区域和掩埋导电层一起构成掩埋位线。

    Method of forming gate conductor structures
    4.
    发明授权
    Method of forming gate conductor structures 有权
    形成栅极导体结构的方法

    公开(公告)号：US08758984B2

    公开(公告)日：2014-06-24

    申请号：US13103108

    申请日：2011-05-09

    申请人： Chang-Ming Wu ,  Yi-Nan Chen ,  Hsien-Wen Liu

    发明人： Chang-Ming Wu ,  Yi-Nan Chen ,  Hsien-Wen Liu

    IPC分类号： H01L21/70

    CPC分类号： H01L21/32139 ,  H01L21/28123 ,  H01L21/28132

    摘要： A method of forming gate conductor structures. A substrate having thereon a gate electrode layer is provided. A multi-layer hard mask is formed overlying the gate electrode layer. The multi-layer hard mask comprises a first hard mask, a second hard mask, and a third hard mask. A photoresist pattern is formed on the multi-layer hard mask. A first etching process is performed to etch the third hard mask, using the photoresist pattern as a first etch resist, thereby forming a patterned third hard mask. A second etching process is performed to etch the second hard mask and the first hard mask, using the patterned third hard mask as a second etch resist, thereby forming a patterned first hard mask. A third etching process is performed to etch a layer of the gate electrode layer, using the patterned first hard mask as a third etch resist.

    摘要翻译： 一种形成栅极导体结构的方法。 提供了具有栅电极层的基板。 形成覆盖栅电极层的多层硬掩模。 多层硬掩模包括第一硬掩模，第二硬掩模和第三硬掩模。 在多层硬掩模上形成光刻胶图形。 执行第一蚀刻工艺以蚀刻第三硬掩模，使用光致抗蚀剂图案作为第一蚀刻抗蚀剂，由此形成图案化的第三硬掩模。 执行第二蚀刻工艺以蚀刻第二硬掩模和第一硬掩模，使用图案化的第三硬掩模作为第二蚀刻抗蚀剂，由此形成图案化的第一硬掩模。 执行第三蚀刻工艺以蚀刻栅极电极层的层，使用图案化的第一硬掩模作为第三蚀刻抗蚀剂。

    Antenna structure
    5.
    发明授权
    Antenna structure 有权
    天线结构

    公开(公告)号：US08692723B2

    公开(公告)日：2014-04-08

    申请号：US13310259

    申请日：2011-12-02

    申请人： Hsien-Wen Liu

    发明人： Hsien-Wen Liu

    IPC分类号： H01Q1/24

    CPC分类号： H01Q1/243 ,  H01Q1/38 ,  H01Q1/48 ,  H01Q7/00

    摘要： An antenna structure includes a circuit board and at least one antenna circuit. The circuit board includes a ground area and an antenna area. The antenna area is substantially rectangular-shaped and arranged between the ground area and the periphery of the circuit board. The antenna circuit is formed within the antenna area and includes a feeding segment, a border segment and at least one ground segment. The feeding segment is connected to the border segment and the distance from the border segment to the periphery of the circuit board ranges from 0 to 3 millimeters; a substantially 90° bent-structure is formed within the border segment. One end portion of the ground segment is connected to the ground area. Thus an antenna structure which enables the antenna circuit to be formed within the remaining space on the periphery of the circuit board is provided.

    摘要翻译： 天线结构包括电路板和至少一个天线电路。 电路板包括接地区域和天线区域。 天线区域基本上是矩形的并且布置在接地区域和电路板的外围之间。 天线电路形成在天线区域内，并包括馈电段，边界段和至少一个地面段。 馈电段连接到边界段，从边界段到电路板周边的距离范围为0至3毫米; 在边界段内形成大致90°的弯曲结构。 接地段的一端连接到接地区域。 因此，提供了使天线电路能够形成在电路板的周边的剩余空间内的天线结构。

    Post-optical proximity correction photoresist pattern collapse rule
    7.
    发明授权
    Post-optical proximity correction photoresist pattern collapse rule 有权
    后光学邻近校正光刻胶图案崩溃规则

    公开(公告)号：US08533638B2

    公开(公告)日：2013-09-10

    申请号：US13079869

    申请日：2011-04-05

    申请人： Kuo Kuei Fu ,  Yi Nan Chen ,  Hsien Wen Liu

    发明人： Kuo Kuei Fu ,  Yi Nan Chen ,  Hsien Wen Liu

    IPC分类号： G06F17/50

    CPC分类号： G03F1/36 ,  G03F1/50

    摘要： A model of defining a photoresist pattern collapse rule is provided. A portion of the photoresist pattern which corresponds to a second line pattern of a photomask layout is defined as non-collapse patterns if d≧5a and c≧1.5b or if 5a>d≧3a and c≧1.2b, wherein b is the widths of two first line patterns, c is the width of a second line pattern of the photomask layout, and a and d are distances between the second line pattern and the two first line patterns. Accordingly, a photomask layout, a semiconductor substrate and a method for improving photoresist pattern collapse for post-optical proximity correction are also provided.

    摘要翻译： 提供了定义光致抗蚀剂图案崩溃规则的模型。 如果d> = 5a且c> = 1.5b或如果5a> d> = 3a且c> = 1.2b，则与光掩模布局的第二线图案对应的光致抗蚀剂图案的一部分被定义为非崩溃图案， 其中b是两个第一线图案的宽度，c是光掩模布局的第二线图案的宽度，a和d是第二线图案和两个第一线图案之间的距离。 因此，还提供了光掩模布局，半导体衬底和用于改善后光学邻近校正的光致抗蚀剂图案崩溃的方法。

    Monitoring pattern, and pattern stitch monitoring method and wafer therewith
    9.
    发明授权
    Monitoring pattern, and pattern stitch monitoring method and wafer therewith 有权
    监测图案，图案针迹监测方法和晶片

    公开(公告)号：US08497568B2

    公开(公告)日：2013-07-30

    申请号：US13079853

    申请日：2011-04-05

    申请人： Kuo Kuei Fu ,  Yi Nan Chen ,  Hsien Wen Liu

    发明人： Kuo Kuei Fu ,  Yi Nan Chen ,  Hsien Wen Liu

    IPC分类号： H01L29/06

    CPC分类号： G03F1/50

    摘要： A monitoring pattern for pattern stitch in double patterning is provided with a plurality of pattern cuts that include at least one line-ended cut and at least one non-line-ended cut, wherein every pattern cut has a stitching critical dimension (CD). A semiconductor wafer having at least one target pattern corresponding to the monitoring pattern is also provided. A method for monitoring pattern stitch can be preformed to check for pattern cut displacement in stitching areas and to increase reliability and printability of layouts, by comparing corresponding stitching critical dimensions of the target pattern and the monitoring pattern.

    摘要翻译： 在双重图案化中的图案针迹的监视模式被提供有多个图案切割，其包括至少一个线端切割和至少一个非线切割，其中每个图案切割具有缝合临界尺寸（CD）。 还提供了具有与监视图案对应的至少一个目标图案的半导体晶片。 可以通过比较目标图案的对应缝合临界尺寸和监测图案，来实现用于监视图案线迹的方法，以检查缝合区域中的图案切割位移并增加布局的可靠性和可印刷性。

    Bonding pad structure for semiconductor devices
    10.
    发明授权
    Bonding pad structure for semiconductor devices 有权
    用于半导体器件的接合焊盘结构

    公开(公告)号：US08476764B2

    公开(公告)日：2013-07-02

    申请号：US13235491

    申请日：2011-09-18

    申请人： Tse-Yao Huang ,  Yi-Nan Chen ,  Hsien-Wen Liu

    发明人： Tse-Yao Huang ,  Yi-Nan Chen ,  Hsien-Wen Liu

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L24/05 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05085 ,  H01L2224/05095 ,  H01L2224/05624

    摘要： A bonding pad structure includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers comprising at least a topmost IMD layer; a bondable metal pad layer disposed on a surface of the topmost IMD layer within a pad forming region; a passivation layer covering a periphery of the bondable metal pad layer and the surface of the topmost IMD layer; and a plurality of via plugs disposed in the topmost IMD layer within an annular region of the pad forming region, wherein the via plugs are not formed in a central region of the pad forming region.

    摘要翻译： 焊盘结构包括其上具有包括至少最上面的IMD层的多个金属间电介质（IMD）层的半导体衬底; 可焊接金属焊盘层，其设置在焊盘形成区域内的最上层IMD层的表面上; 覆盖可焊接金属焊盘层的周边和最上面的IMD层的表面的钝化层; 以及多个通孔插塞，其设置在焊盘形成区域的环形区域内的最上层的IMD层中，其中通孔插塞不形成在焊盘形成区域的中心区域中。