公开(公告)号：US20110260230A1

公开(公告)日：2011-10-27

申请号：US12829674

申请日：2010-07-02

申请人： TZUNG HAN LEE ,  CHUNG-LIN HUANG ,  HSIEN-WEN LIU

发明人： TZUNG HAN LEE ,  CHUNG-LIN HUANG ,  HSIEN-WEN LIU

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/10891 ,  H01L21/26586 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7827

摘要： A memory cell with surrounding word line structures includes an active area; a plurality of first trenches formed on the active area in a first direction, each first trench has a bit line on a sidewall therein; a plurality of second trenches formed on the active area in a second direction, each second trench has two word lines formed correspondingly on the sidewalls in the second trench; and a plurality of transistors formed on the active area. The word line pairs are arranged into a surrounding word line structure. The transistor is controlled by the bit line and the two word lines, thus improving the speed of the transistor.

摘要翻译： 具有周围字线结构的存储单元包括有源区; 在第一方向上形成在有源区上的多个第一沟槽，每个第一沟槽在其侧壁上具有位线; 在第二方向上形成在有源区上的多个第二沟槽，每个第二沟槽具有相应地形成在第二沟槽中的侧壁上的两条字线; 以及形成在有源区上的多个晶体管。 字线对被排列成周围的字线结构。 晶体管由位线和两个字线控制，从而提高晶体管的速度。

公开(公告)号：US20120012905A1

公开(公告)日：2012-01-19

申请号：US12899721

申请日：2010-10-07

申请人： TZUNG HAN LEE ,  CHUNG-LIN HUANG ,  HSIEN-WEN LIU

发明人： TZUNG HAN LEE ,  CHUNG-LIN HUANG ,  HSIEN-WEN LIU

IPC分类号： H01L29/772 ,  H01L21/335

CPC分类号： H01L21/76224 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66621 ,  H01L29/78

摘要： A semiconductor device is disclosed which includes a silicide substrate, a nitride layer, two STIs, and a strain nitride. The silicide substrate has two doping areas. The nitride layer is deposited on the silicide substrate. The silicide substrate and the nitride layer have a recess running through. The two doping areas are at two sides of the recess. The end of the recess has an etching space bigger than the recess. The top of the silicide substrate has a fin-shaped structure. The two STIs are at the two opposite sides of the silicide substrate (recess). The strain nitride is spacer-formed in the recess and attached to the side wall of the silicide substrate, nitride layer, two STIs. The two doping areas cover the strain nitride. As a result, the efficiency of semiconductor is improved, and the drive current is increased.

摘要翻译： 公开了一种半导体器件，其包括硅化物衬底，氮化物层，两个STI和应变氮化物。 硅化物衬底具有两个掺杂区域。 氮化物层沉积在硅化物衬底上。 硅化物衬底和氮化物层具有贯穿的凹槽。 两个掺杂区位于凹槽的两侧。 凹部的端部具有比凹部大的蚀刻空间。 硅化物衬底的顶部具有鳍状结构。 两个STI位于硅化物衬底（凹槽）的两个相对侧。 应变氮化物在凹槽​​中间隔形成并附着到硅化物衬底，氮化物层，两个STI的侧壁上。 两个掺杂区域覆盖了应变氮化物。 结果，提高了半导体的效率，并且提高了驱动电流。

公开(公告)号：US20120193706A1

公开(公告)日：2012-08-02

申请号：US13039523

申请日：2011-03-03

申请人： TZUNG HAN LEE ,  CHUNG-YUAN LEE ,  HSIEN-WEN LIU

发明人： TZUNG HAN LEE ,  CHUNG-YUAN LEE ,  HSIEN-WEN LIU

IPC分类号： H01L27/088 ,  H01L21/8239

CPC分类号： H01L27/10802 ,  H01L29/7841

摘要： A manufacturing method for a vertical transistor of random-access memory, having the steps of: defining an active region on a semiconductor substrate; forming a shallow trench isolation structure outside of the active region; etching the active region and forming a gate dielectric layer and a positioning gate thereon, forming a word line perpendicular to the positioning gate; forming spacing layers on the outer surfaces of the word line; implanting ions to the formed structure in forming an n-type and a p-type region on opposite sides of the word line with the active region; forming an n-type and a p-type floating body respectively on the n-type and p-type region; forming a source line perpendicular to the word line and connecting to the n-type floating body; forming a bit line perpendicular to the source line and connecting to the p-type floating body. Hence, a vertical transistor with steady threshold voltage is achieved.

摘要翻译： 一种用于随机存取存储器的垂直晶体管的制造方法，具有以下步骤：在半导体衬底上限定有源区; 在活性区域外形成浅沟槽隔离结构; 蚀刻有源区并在其上形成栅介电层和定位栅，形成垂直于定位栅的字线; 在字线的外表面上形成间隔层; 将离子注入所形成的结构中，以在所述有源区域的字线的相对侧上形成n型和p型区域; 在n型和p型区域分别形成n型和p型浮体; 形成垂直于字线并连接到n型浮体的源极线; 形成垂直于源极线并连接到p型浮体的位线。 因此，实现了具有稳定阈值电压的垂直晶体管。

公开(公告)号：US20130026556A1

公开(公告)日：2013-01-31

申请号：US13224561

申请日：2011-09-02

申请人： TZUNG HAN LEE ,  CHUNG-LIN HUANG ,  RON FU CHU

发明人： TZUNG HAN LEE ,  CHUNG-LIN HUANG ,  RON FU CHU

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L29/42328 ,  H01L29/7887

摘要： A NAND type flash memory for increasing data read/write reliability includes a semiconductor substrate unit, a base unit, and a plurality of data storage units. The semiconductor substrate unit includes a semiconductor substrate. The base unit includes a first dielectric layer formed on the semiconductor substrate. The data storage units are formed on the first dielectric layer. Each data storage unit includes two floating gates formed on the first dielectric layer, two inter-gate dielectric layers respectively formed on the two floating gates, two control gates respectively formed on the two inter-gate dielectric layers, a second dielectric layer formed on the first dielectric layer, between the two floating gates, between the two inter-gate dielectric layers, and between the two control gates, and a third dielectric layer formed on the first dielectric layer and surrounding and connecting with the two floating gates, the two inter-gate dielectric layers, and the two control gates.

摘要翻译： 用于增加数据读/写可靠性的NAND型闪速存储器包括半导体衬底单元，基本单元和多个数据存储单元。 半导体衬底单元包括半导体衬底。 基座单元包括形成在半导体衬底上的第一电介质层。 数据存储单元形成在第一电介质层上。 每个数据存储单元包括形成在第一介电层上的两个浮置栅极，分别形成在两个浮置栅极上的两个栅极间电介质层，分别形成在两个栅极间电介质层上的两个控制栅极， 第一电介质层，两个浮置栅极之间，两个栅极间电介质层之间以及两个控制栅极之间，以及形成在第一介电层上并围绕并连接两个浮动栅极的第三介质层， - 门电介质层和两个控制门。

公开(公告)号：US20110053337A1

公开(公告)日：2011-03-03

申请号：US12827082

申请日：2010-06-30

申请人： CHIEN-HSUN CHEN ,  TZUNG HAN LEE ,  CHUNG-LIN HUANG

发明人： CHIEN-HSUN CHEN ,  TZUNG HAN LEE ,  CHUNG-LIN HUANG

IPC分类号： H01L21/762

CPC分类号： H01L27/10876 ,  H01L21/76224 ,  H01L27/10894

摘要： A self-alignment method for a recess channel dynamic random access memory includes providing a substrate with a target layer, a barrier layer and a lining layer, wherein the target layer has shallow trench isolation structures; patternizing the lining layer, barrier layer and target layer to form recess trench channels; depositing a dielectric layer onto the recess trench channel; forming an ion doped region in the target layer; removing a portion of the dielectric layer to expose a portion of the recess trench channel; forming a filler layer covered onto the recess trench channel; removing a portion of the filler layer to expose a portion of the recess trench channel; forming a passivation layer onto the recess trench channel; removing the passivation layer on the lining layer; and removing the lining layer to form a plurality of structural monomers disposed at the recess trench channel and protruded from the target layer.

摘要翻译： 用于凹槽通道动态随机存取存储器的自对准方法包括：提供具有目标层，阻挡层和衬里层的衬底，其中所述目标层具有浅沟槽隔离结构; 图案化衬里层，阻挡层和目标层以形成凹槽沟道; 将介电层沉积到凹槽沟道上; 在靶层中形成离子掺杂区; 去除所述电介质层的一部分以暴露所述凹槽沟槽沟道的一部分; 形成覆盖在所述凹槽沟道上的填充层; 去除所述填充层的一部分以暴露所述凹槽沟道的一部分; 在所述凹槽沟道上形成钝化层; 去除衬里层上的钝化层; 并且移除所述衬里层以形成设置在所述凹槽沟道处并从所述目标层突出的多个结构单体。

公开(公告)号：US20130062674A1

公开(公告)日：2013-03-14

申请号：US13282771

申请日：2011-10-27

申请人： TZUNG HAN LEE ,  CHUNG-LIN HUANG ,  RON FU CHU

发明人： TZUNG HAN LEE ,  CHUNG-LIN HUANG ,  RON FU CHU

IPC分类号： H01L29/82

CPC分类号： H01L27/228 ,  G11C11/161 ,  G11C11/1659 ,  H01L43/08

摘要： A spin transfer torque random access memory includes a substance unit, a source line unit, an insulation unit, a transistor unit, a MTJ unit, and a bit line unit. The substance unit includes a substance layer. The source line unit includes a plurality of source lines formed inside the substance layer. The transistor unit includes a plurality of transistors respectively disposed on the source lines. Each transistor includes a source region formed on each corresponding source line, a drain region formed above the source region, a channel region formed between the source region and the drain region, and a surrounding gate region surrounding the source region, the drain region, and the channel region. The MTJ unit includes a plurality of MTJ structures respectively disposed on the transistors. The bit line unit includes at least one bit line disposed on the MTJ unit.

摘要翻译： 自旋传递转矩随机存取存储器包括物质单元，源极线单元，绝缘单元，晶体管单元，MTJ单元和位线单元。 物质单元包括物质层。 源极线单元包括形成在物质层内部的多个源极线。 晶体管单元包括分别设置在源极线上的多个晶体管。 每个晶体管包括形成在每个对应源极线上的源极区域，形成在源极区域上方的漏极区域，形成在源极区域和漏极区域之间的沟道区域，以及围绕源极区域，漏极区域和 通道区域。 MTJ单元包括分别设置在晶体管上的多个MTJ结构。 位线单元包括设置在MTJ单元上的至少一个位线。

公开(公告)号：US20130029465A1

公开(公告)日：2013-01-31

申请号：US13240011

申请日：2011-09-22

申请人： TZUNG HAN LEE ,  CHUNG-LIN HUANG ,  RON FU CHU

发明人： TZUNG HAN LEE ,  CHUNG-LIN HUANG ,  RON FU CHU

IPC分类号： H01L21/336

CPC分类号： H01L27/10891 ,  H01L21/26586 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/66545 ,  H01L29/66621

摘要： The instant disclosure relates to a manufacturing method of memory structure for dynamic random-access memory (DRAM). The method includes the steps of: (a) providing a substrate having a plurality of parallel trenches formed on a planar surface thereof each defining a buried gate, where a first insulating layer is formed on the planar surface of the substrate; (b) forming a gate oxide layer on the surface of each trench that defines the buried gate; (c) disposing a metal filler on the gate oxide layer to fill each of the trenches; (d) removing the metal filler in the upper region of each trench to selectively expose the gate oxide layer; (e) implanting ions at an oblique angle toward the exposed portions of the gate oxide layer in each trench to respectively form a drain electrode and a source electrode in the substrate abreast the gate oxide layer.

摘要翻译： 本公开涉及用于动态随机存取存储器（DRAM）的存储器结构的制造方法。 该方法包括以下步骤：（a）提供具有形成在其平坦表面上的多个平行沟槽的衬底，每个限定掩埋栅极，其中第一绝缘层形成在衬底的平面表面上; （b）在限定所述掩埋栅极的每个沟槽的表面上形成栅氧化层; （c）在栅极氧化物层上设置金属填料以填充每个沟槽; （d）去除每个沟槽的上部区域中的金属填料以选择性地暴露栅极氧化物层; （e）以倾斜角度将离子注入每个沟槽中的栅极氧化层的暴露部分，以分别形成衬底中的漏电极和源电极，并与栅极氧化物层并排。

公开(公告)号：US20110127574A1

公开(公告)日：2011-06-02

申请号：US12758252

申请日：2010-04-12

申请人： SHIN BIN HUANG ,  CHUNG-LIN HUANG ,  CHING-NAN HSIAO ,  TZUNG HAN LEE

发明人： SHIN BIN HUANG ,  CHUNG-LIN HUANG ,  CHING-NAN HSIAO ,  TZUNG HAN LEE

IPC分类号： H01L27/108 ,  H01L27/06

CPC分类号： H01L27/0259

摘要： A device for preventing current-leakage is located between a transistor and a capacitor of a memory cell. The two terminals of the device for preventing current-leakage are respectively connected with a slave terminal of the transistor and an electric pole of the capacitor. The device for preventing current-leakage has at least two p-n junctions. The device for preventing current-leakage is a lateral silicon controlled rectifier, a diode for alternating current, or a silicon controlled rectifier. By utilizing the driving characteristic of the device for preventing current-leakage, electric charge stored in the capacitor hardly passes through the device for preventing current-leakage when the transistor is turned off to improve the current-leakage problem.

摘要翻译： 用于防止漏电的装置位于存储单元的晶体管和电容器之间。 用于防止漏电的装置的两个端子分别与晶体管的从端和电容器的电极连接。 用于防止漏电的装置具有至少两个p-n结。 用于防止漏电的装置是侧向可控硅整流器，用于交流电流的二极管或可控硅整流器。 通过利用用于防止漏电的装置的驱动特性，存储在电容器中的电荷几乎不会通过用于防止晶体管截止时漏电的装置，从而改善漏电问题。

公开(公告)号：US20130026554A1

公开(公告)日：2013-01-31

申请号：US13196037

申请日：2011-08-02

申请人： TZUNG HAN LEE ,  CHUNG-LIN HUANG ,  RON FU CHU

发明人： TZUNG HAN LEE ,  CHUNG-LIN HUANG ,  RON FU CHU

IPC分类号： H01L29/788

CPC分类号： H01L29/7887 ,  H01L27/11521

摘要： A NAND type flash memory for increasing data read/write reliability includes a semiconductor substrate unit, a base unit, and a plurality of data storage units. The semiconductor substrate unit includes a semiconductor substrate. The base unit includes a first dielectric layer formed on the semiconductor substrate. The data storage units are adjacent to each other and formed on the first dielectric layer. Each data storage unit includes at least two floating gates formed on the first dielectric layer, a second dielectric layer formed on the first dielectric layer and between the two floating gates, an inter-gate dielectric layer formed on the two floating gates and the second dielectric layer, at least one control gate formed on the inter-gate dielectric layer, and a third dielectric layer formed on the first dielectric layer and surrounding and tightly connecting with the two floating gates, the inter-gate dielectric layer, and the control gate.

摘要翻译： 用于增加数据读/写可靠性的NAND型闪速存储器包括半导体衬底单元，基本单元和多个数据存储单元。 半导体衬底单元包括半导体衬底。 基座单元包括形成在半导体衬底上的第一电介质层。 数据存储单元彼此相邻并形成在第一介电层上。 每个数据存储单元包括形成在第一介电层上的至少两个浮动栅极，形成在第一介电层上和两个浮置栅极之间的第二介电层，形成在两个浮置栅极和第二电介质层上的栅极间电介质层 形成在所述栅极间电介质层上的至少一个控制栅极以及形成在所述第一电介质层上并且与所述两个浮置栅极，所述栅极间介电层和所述控制栅极包围并紧密连接的第三电介质层。