Invention Application
US20120025396A1 SEMICONDUCTOR DEVICE WITH DIE STACK ARRANGEMENT INCLUDING STAGGERED DIE AND EFFICIENT WIRE BONDING
有权
具有DIE堆叠布置的半导体器件，包括插入式和有效的电线接合
- Patent Title: SEMICONDUCTOR DEVICE WITH DIE STACK ARRANGEMENT INCLUDING STAGGERED DIE AND EFFICIENT WIRE BONDING
- Patent Title (中): 具有DIE堆叠布置的半导体器件，包括插入式和有效的电线接合
-
Application No.: US12844959Application Date: 2010-07-28
-
Publication No.: US20120025396A1Publication Date: 2012-02-02
- Inventor: Chih-Chin Liao , Cheeman Yu , Ya Huei Lee
- Applicant: Chih-Chin Liao , Cheeman Yu , Ya Huei Lee
- Main IPC: H01L23/488
- IPC: H01L23/488
Abstract:
A semiconductor die package is disclosed. An example of the semiconductor package includes a first group of semiconductor die interspersed with a second group of semiconductor die. The die from the first and second groups are offset from each other along a first axis and staggered with respect to each other along a second axis orthogonal to the first axis. A second example of the semiconductor package includes an irregular shaped edge and a wire bond to the substrate from a semiconductor die above the lowermost semiconductor die in the package.
Public/Granted literature
- US08415808B2 Semiconductor device with die stack arrangement including staggered die and efficient wire bonding Public/Granted day:2013-04-09
Information query
IPC分类:
