Invention Application
- Patent Title: WRITE-LEVELING IMPLEMENTATION IN PROGRAMMABLE LOGIC DEVICES
- Patent Title (中): 可编程逻辑器件中的写层次实现
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Application No.: US13349228Application Date: 2012-01-12
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Publication No.: US20120106264A1Publication Date: 2012-05-03
- Inventor: Yan Chong , Bonnie I. Wang , Chiakang Sung , Joseph Huang , Michael H.M. Chu
- Applicant: Yan Chong , Bonnie I. Wang , Chiakang Sung , Joseph Huang , Michael H.M. Chu
- Applicant Address: US CA San Jose
- Assignee: ALTERA CORPORATION
- Current Assignee: ALTERA CORPORATION
- Current Assignee Address: US CA San Jose
- Main IPC: G11C7/10
- IPC: G11C7/10 ; H03L7/00 ; G11C7/22

Abstract:
Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device.
Public/Granted literature
- US08671303B2 Write-leveling implementation in programmable logic devices Public/Granted day:2014-03-11
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