Invention Application
US20120112943A1 SIGMA-DELTA MODULATOR WITH SAR ADC AND TRUNCATER HAVING ORDER LOWER THAN ORDER OF INTEGRATOR AND RELATED SIGMA-DELTA MODULATION METHOD
有权
具有SAR ADC和TRANCATER的SIGMA-DELTA调制器低于集成器和相关SIGMA-DELTA调制方法的顺序
- Patent Title: SIGMA-DELTA MODULATOR WITH SAR ADC AND TRUNCATER HAVING ORDER LOWER THAN ORDER OF INTEGRATOR AND RELATED SIGMA-DELTA MODULATION METHOD
- Patent Title (中): 具有SAR ADC和TRANCATER的SIGMA-DELTA调制器低于集成器和相关SIGMA-DELTA调制方法的顺序
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Application No.: US13072797Application Date: 2011-03-28
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Publication No.: US20120112943A1Publication Date: 2012-05-10
- Inventor: Yu-Hsin Lin , Hung-Chieh Tsai , Sheng-Jui Huang
- Applicant: Yu-Hsin Lin , Hung-Chieh Tsai , Sheng-Jui Huang
- Main IPC: H03M3/02
- IPC: H03M3/02

Abstract:
A sigma-delta modulator includes a processing circuit, a quantizer, a truncater and a feedback circuit. The processing circuit receives an input signal and an analog information and generates an integrated signal by perform an integration upon a difference between the input signal and the analog information. The quantizer includes a successive approximation register (SAR) analog-to-digital converter (ADC) for receiving the integrated signal and generating a digital information according to the integrated signal. The truncater receives the digital information and generates a truncated information according to the digital information. The feedback circuit generates the analog information to the processing circuit according to the truncated information, wherein an order of the truncater is lower than an order of the integration.
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