-
公开(公告)号：US20180006661A1
公开(公告)日：2018-01-04
申请号：US15703840
申请日：2017-09-13
Applicant: Sheng-Jui Huang , Nathan Egan , Divya Kesharwani , Michael A. Ashburn, JR. , Frank Op 't Eynde
Inventor： Sheng-Jui Huang , Nathan Egan , Divya Kesharwani , Michael A. Ashburn, JR. , Frank Op 't Eynde
IPC: H03M3/00
Abstract: According to at least one aspect, a delta sigma modulator circuit is provided. The delta sigma modulator circuit includes a first signal processor circuit configured to receive an input signal and a feedback signal and generate a processed signal using the input signal and the feedback signal, a quantizer configured to generate a digital code using the processed signal, a second signal processor circuit configured to receive the digital code, segment the digital code to form a segmented digital code that is smaller in size than the digital code, and generate a rotated digital code using the segmented digital code at least in part by rotating the segmented digital code to compensate for an excess loop delay in the circuit, and an digital-to-analog converter (DAC) configured to receive the rotated digital code and generate the feedback signal using the rotated digital code.
-
2.发明申请SIGMA-DELTA MODULATOR WITH SAR ADC AND TRUNCATER HAVING ORDER LOWER THAN ORDER OF INTEGRATOR AND RELATED SIGMA-DELTA MODULATION METHOD 有权具有SAR ADC和TRANCATER的SIGMA-DELTA调制器低于集成器和相关SIGMA-DELTA调制方法的顺序公开(公告)号：US20120112943A1
公开(公告)日：2012-05-10
申请号：US13072797
申请日：2011-03-28
Applicant: Yu-Hsin Lin , Hung-Chieh Tsai , Sheng-Jui Huang
Inventor： Yu-Hsin Lin , Hung-Chieh Tsai , Sheng-Jui Huang
IPC: H03M3/02
CPC classification number: H03M3/30 , H03M3/412 , H03M3/426 , H03M7/3042
Abstract: A sigma-delta modulator includes a processing circuit, a quantizer, a truncater and a feedback circuit. The processing circuit receives an input signal and an analog information and generates an integrated signal by perform an integration upon a difference between the input signal and the analog information. The quantizer includes a successive approximation register (SAR) analog-to-digital converter (ADC) for receiving the integrated signal and generating a digital information according to the integrated signal. The truncater receives the digital information and generates a truncated information according to the digital information. The feedback circuit generates the analog information to the processing circuit according to the truncated information, wherein an order of the truncater is lower than an order of the integration.
Abstract translation: Σ-Δ调制器包括处理电路，量化器，截短器和反馈电路。 处理电路接收输入信号和模拟信息，并通过根据输入信号和模拟信息之间的差进行积分来产生积分信号。 量化器包括用于接收积分信号并根据积分信号产生数字信息的逐次逼近寄存器（SAR）模拟 - 数字转换器（ADC）。 截断器接收数字信息并根据数字信息产生截断的信息。 反馈电路根据截断的信息向处理电路生成模拟信息，其中截断器的顺序低于积分的顺序。
-
公开(公告)号：US07872599B2
公开(公告)日：2011-01-18
申请号：US12328786
申请日：2008-12-05
Applicant: Sheng-Jui Huang
Inventor： Sheng-Jui Huang
IPC: H03M3/00
CPC classification number: H03F3/45192 , H03F1/26 , H03F2200/372 , H03F2203/45301 , H03F2203/45724
Abstract: A loading stage for outputting an amplified differential output, including: a noise source inducing noises originally located in a first frequency band, and a first modulating device coupled to the noise source for modulating the noises into a second frequency band from the first frequency band.
Abstract translation: 一种用于输出放大的差分输出的加载阶段，包括：源自原来位于第一频带中的噪声源，以及耦合到噪声源的第一调制装置，用于将噪声调制成来自第一频带的第二频带。
-
4.发明授权Processing apparatus for calibrating analog filter according to frequency-related characteristic of analog filter, processing apparatus for generating compensation parameter used to calibrate analog filter, related communication device, and methods thereof 有权用于根据模拟滤波器的频率相关特性校准模拟滤波器的处理装置，用于产生用于校准模拟滤波器的补偿参数的处理装置，相关通信装置及其方法公开(公告)号：US07859439B2
公开(公告)日：2010-12-28
申请号：US12420026
申请日：2009-04-07
Applicant: Pei-Wei Chen , Sheng-Jui Huang
Inventor： Pei-Wei Chen , Sheng-Jui Huang
IPC: H03M1/10
CPC classification number: H04B1/0035 , H03H7/0153 , H03H7/03
Abstract: A processing apparatus for calibrating an analog filter of a communication device in a digital domain is disclosed, wherein the analog filter is arranged to perform a filtering operation upon a communication signal in an analog domain. The processing apparatus includes a signal processing circuit and a digital filter. The signal processing circuit is used for transforming the communication signal between the digital domain and the analog domain. The digital filter is coupled to the signal processing circuit, and used for performing a filtering operation upon the communication signal in the digital domain, wherein a frequency response of the digital filter is arranged to compensate a frequency response of the analog filter according to at least a compensation parameter generated with reference to a frequency-related characteristic of the analog filter.
Abstract translation: 公开了一种用于校准数字域中的通信设备的模拟滤波器的处理装置，其中模拟滤波器被布置为对模拟域中的通信信号执行滤波操作。 处理装置包括信号处理电路和数字滤波器。 信号处理电路用于对数字域和模拟域之间的通信信号进行变换。 数字滤波器耦合到信号处理电路，并用于对数字域中的通信信号执行滤波操作，其中数字滤波器的频率响应被布置成至少根据模拟滤波器的频率响应来补偿 参考模拟滤波器的频率相关特性产生的补偿参数。
-
公开(公告)号：US20080018510A1
公开(公告)日：2008-01-24
申请号：US11778645
申请日：2007-07-16
Applicant: Sheng-Jui Huang
Inventor： Sheng-Jui Huang
CPC classification number: H03F3/45192 , H03F1/26 , H03F2200/372 , H03F2203/45301 , H03F2203/45724
Abstract: An operational amplifier is disclosed. The operational amplifier comprises an input stage and a loading stage. The input stage receives a differential input signal pair corresponding to a first frequency band. The loading stage is coupled to the input stage. The loading stage outputs an amplified differential output at output nodes. The loading stage comprises a flicker noise source and a modulating device. The modulating device is coupled to the flicker noise source. The modulating device modulates flicker noises into a second frequency band. The modulating device is not within a signal path.
Abstract translation: 公开了一种运算放大器。 运算放大器包括输入级和加载级。 输入级接收对应于第一频带的差分输入信号对。 加载阶段耦合到输入级。 加载级在输出节点输出放大的差分输出。 加载阶段包括闪烁噪声源和调制装置。 调制装置耦合到闪烁噪声源。 调制装置将闪烁噪声调制成第二频带。 调制装置不在信号路径内。
-
Patent Agency Ranking
公开(公告)号：US10075181B2
公开(公告)日：2018-09-11
申请号：US15703840
申请日：2017-09-13
Applicant: Sheng-Jui Huang , Nathan Egan , Divya Kesharwani , Michael A. Ashburn, Jr. , Frank Op 't Eynde
Inventor： Sheng-Jui Huang , Nathan Egan , Divya Kesharwani , Michael A. Ashburn, Jr. , Frank Op 't Eynde
IPC: H03M3/00
Abstract: According to at least one aspect, a delta sigma modulator circuit is provided. The delta sigma modulator circuit includes a first signal processor circuit configured to receive an input signal and a feedback signal and generate a processed signal using the input signal and the feedback signal, a quantizer configured to generate a digital code using the processed signal, a second signal processor circuit configured to receive the digital code, segment the digital code to form a segmented digital code that is smaller in size than the digital code, and generate a rotated digital code using the segmented digital code at least in part by rotating the segmented digital code to compensate for an excess loop delay in the circuit, and an digital-to-analog converter (DAC) configured to receive the rotated digital code and generate the feedback signal using the rotated digital code.
-
公开(公告)号：US20120319881A1
公开(公告)日：2012-12-20
申请号：US13450866
申请日：2012-04-19
Applicant: Sheng-Jui Huang , Chen-Yen Ho
Inventor： Sheng-Jui Huang , Chen-Yen Ho
IPC: H03M3/04
Abstract: A sigma-delta modulator includes a front portion and a hybrid portion to form a loop filter. The front portion includes integrator(s) and feed-forward path(s), and is arranged to provide a front signal by combining signals of the integrator(s) and feed-forward path(s). The hybrid portion is coupled to the front portion, and arranged to provide a filtered signal by combining an integration of the front signal and a weighting of the front signal. The filtered signal is quantized, converted from digital to analog, and fed back to the loop filter.
Abstract translation: Σ-Δ调制器包括前部和混合部分以形成环路滤波器。 前部包括积分器和前馈路径，并且被布置成通过组合积分器和前馈路径的信号来提供前信号。 混合部分耦合到前部，并且被布置成通过组合前信号的积分和前信号的加权来提供滤波信号。 经滤波的信号被量化，从数字转换为模拟，并反馈到环路滤波器。
-
8.发明申请METHODS FOR SHIFTING COMMON MODE BETWEEN DIFFERENT POWER DOMAINS AND APPARATUS THEREOF 审中-公开移动不同功率域之间的通用模式的方法及其设备公开(公告)号：US20090243392A1
公开(公告)日：2009-10-01
申请号：US12056291
申请日：2008-03-27
Applicant: Sheng-Jui Huang
Inventor： Sheng-Jui Huang
CPC classification number: H03M1/0604 , H03F1/30 , H03F3/187 , H03F3/213 , H03F3/347 , H03F2203/45112 , H03F2203/45292 , H03M1/12 , H03M1/66 , Y10T307/675
Abstract: A signal processing system having different power domains is provided. The signal processing system has a first amplifier circuit operating under a first power domain; a second amplifier circuit operating under a second power domain and having a feedback configuration; a first impedance unit, coupled between an output node of the first amplifier circuit and a first input node of the second amplifier circuit; and a bias current generating circuit, coupled to the first input node of the second amplifier circuit, for providing a bias current to thereby reduce a DC current flowing through a feedback path of the second amplifier unit.
Abstract translation: 提供具有不同功率域的信号处理系统。 信号处理系统具有在第一功率域下工作的第一放大器电路; 第二放大器电路，其在第二功率域下工作并具有反馈配置; 第一阻抗单元，耦合在第一放大器电路的输出节点和第二放大器电路的第一输入节点之间; 以及耦合到第二放大器电路的第一输入节点的偏置电流产生电路，用于提供偏置电流，从而减少流过第二放大器单元的反馈路径的直流电流。
-
公开(公告)号：US20090079608A1
公开(公告)日：2009-03-26
申请号：US12328786
申请日：2008-12-05
Applicant: Sheng-Jui Huang
Inventor： Sheng-Jui Huang
IPC: H03M3/00
CPC classification number: H03F3/45192 , H03F1/26 , H03F2200/372 , H03F2203/45301 , H03F2203/45724
Abstract: A loading stage for outputting an amplified differential output, including: a noise source inducing noises originally located in a first frequency band, and a first modulating device coupled to the noise source for modulating the noises into a second frequency band from the first frequency band.
Abstract translation: 一种用于输出放大的差分输出的加载阶段，包括：源自原来位于第一频带中的噪声源，以及耦合到噪声源的第一调制装置，用于将噪声调制成来自第一频带的第二频带。
-
10.发明授权公开(公告)号：US08552894B2
公开(公告)日：2013-10-08
申请号：US13450866
申请日：2012-04-19
Applicant: Sheng-Jui Huang , Chen-Yen Ho
Inventor： Sheng-Jui Huang , Chen-Yen Ho
IPC: H03M3/00
Abstract: A sigma-delta modulator includes a front portion and a hybrid portion to form a loop filter. The front portion includes integrator(s) and feed-forward path(s), and is arranged to provide a front signal by combining signals of the integrator(s) and feed-forward path(s). The hybrid portion is coupled to the front portion, and arranged to provide a filtered signal by combining an integration of the front signal and a weighting of the front signal. The filtered signal is quantized, converted from digital to analog, and fed back to the loop filter.
Abstract translation: Σ-Δ调制器包括前部和混合部分以形成环路滤波器。 前部包括积分器和前馈路径，并且被布置成通过组合积分器和前馈路径的信号来提供前信号。 混合部分耦合到前部，并且被布置成通过组合前信号的积分和前信号的加权来提供滤波信号。 经滤波的信号被量化，从数字转换为模拟，并反馈到环路滤波器。
-
-
-
-
-
-
-
-
-
Search Results
22
records
(took 0.016 seconds)
